===================================================================
@@ -2769,7 +2769,8 @@ vect_analyze_data_ref_accesses (vec_info
/* If init_b == init_a + the size of the type * k, we have an
interleaving, and DRA is accessed before DRB. */
HOST_WIDE_INT type_size_a = tree_to_uhwi (sza);
- if ((init_b - init_a) % type_size_a != 0)
+ if (type_size_a == 0
+ || (init_b - init_a) % type_size_a != 0)
break;
/* If we have a store, the accesses are adjacent. This splits
===================================================================
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+
+typedef struct
+{
+} st1;
+
+typedef struct
+{
+ volatile int c;
+} __attribute__ ((aligned (4))) st2;
+
+struct s4
+{
+ st1 f1;
+ st2 f2;
+ st1 f3;
+};
+
+struct s3;
+
+void
+foo (struct s3 *arg, struct s4 *arg1)
+{
+ arg1->f1 = (st1) { };
+ arg1->f3 = (st1) { };
+}