From patchwork Thu Aug 9 15:00:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Monakov X-Patchwork-Id: 955691 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-483460-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ispras.ru Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="HV12mgHy"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41mWfv0nC7z9s4Z for ; Fri, 10 Aug 2018 01:01:26 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=aauCL6sexk+IKQJ47bFQ5pTOqYgWUA1T2k4Ra8mshk8jltPOWQ gjF1pQnXpd9x45ZhYBh5sGEiDvOGjIfpRFsI9kw0ixCS+14z304yMymgs4fOkFyk uDVxL37H68Txjer6trJh6u+pTUqPTNdtsigQXrTODcMxPvp0+sJ5VQN/s= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=EYoChCvBb96ykQj8CaP6ptT7bJM=; b=HV12mgHyGziNq/6EVmaE 7/chwqhaNxcg5WrpFDK0v00FGbK+bmfVGA6kcULMzuJyxkT+iHYBWgkBljWUDiw+ iUFVPJzrVpNtrN0MW6wqeJ5Ibyh7zmanF4dNwMzu+umqM/Hu9QfpF4mDtdG/gft0 rV/V9fTTbggc8DnlWKpyxic= Received: (qmail 110029 invoked by alias); 9 Aug 2018 15:01:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 109609 invoked by uid 89); 9 Aug 2018 15:00:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS, TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=H*M:intra, fits, Hx-languages-length:2450, offer X-HELO: smtp.ispras.ru Received: from bran.ispras.ru (HELO smtp.ispras.ru) (83.149.199.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 09 Aug 2018 15:00:25 +0000 Received: from monopod.intra.ispras.ru (monopod.intra.ispras.ru [10.10.3.121]) by smtp.ispras.ru (Postfix) with ESMTP id AD7A5203B2; Thu, 9 Aug 2018 18:00:05 +0300 (MSK) Date: Thu, 9 Aug 2018 18:00:05 +0300 (MSK) From: Alexander Monakov To: gcc-patches@gcc.gnu.org cc: Uros Bizjak Subject: [PATCH] i386: do not use SImode mul-highpart on 64-bit Message-ID: User-Agent: Alpine 2.20.13 (LNX 116 2015-12-14) MIME-Version: 1.0 Hello, on x86-64, 32-bit division by constants uses mulsi3_highpart pattern that turns into 'mull ' instruction with source implicitly in eax and result in edx:eax. However, using 64-bit multiplication with zero-extended source would be preferable, as the imulq instruction accepts the magic multiplier as immediate if it fits into 31 bits, has fewer register allocation constraints, and typically has better latency/throughput. Perhaps ideally we'd want expand_divmod to automatically choose this cheaper variant on x86, but changing that appears to be too complicated. On the other hand, we don't use mul_highpart patterns for anything else, so we can simply expose only the DImode mul_highpart on x86-64. This patch does that by changing mode iterator so we offer only SImode mul-highpart on 32-bit x86 and only DImode on 64-bit. Bootstrapped/regtested on x86-64, OK for trunk? Alexander PR target/82418 * config/i386/i386.md (mul3_highpart): Use DWIH mode iterator instead of SWI48. testsuite/ * gcc.target/i386/pr82418.c: New test. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 73948c12618..10783d305d2 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -7792,16 +7792,16 @@ (define_insn "*mulqihi3_1" (set_attr "mode" "QI")]) (define_expand "mul3_highpart" - [(parallel [(set (match_operand:SWI48 0 "register_operand") - (truncate:SWI48 + [(parallel [(set (match_operand:DWIH 0 "register_operand") + (truncate:DWIH (lshiftrt: (mult: (any_extend: - (match_operand:SWI48 1 "nonimmediate_operand")) + (match_operand:DWIH 1 "nonimmediate_operand")) (any_extend: - (match_operand:SWI48 2 "register_operand"))) + (match_operand:DWIH 2 "register_operand"))) (match_dup 3)))) - (clobber (match_scratch:SWI48 4)) + (clobber (match_scratch:DWIH 4)) (clobber (reg:CC FLAGS_REG))])] "" "operands[3] = GEN_INT (GET_MODE_BITSIZE (mode));") diff --git a/gcc/testsuite/gcc.target/i386/pr82418.c b/gcc/testsuite/gcc.target/i386/pr82418.c index e69de29bb2d..95a506d5ccd 100644 --- a/gcc/testsuite/gcc.target/i386/pr82418.c +++ b/gcc/testsuite/gcc.target/i386/pr82418.c @@ -0,0 +1,10 @@ +/* PR target/82418 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "imul\[^\n\r]*1374389535" } } */ + +unsigned +f1(unsigned x) +{ + return x / 100; +}