From patchwork Fri May 26 18:48:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Monakov X-Patchwork-Id: 767514 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wZFXv28zzz9rxm for ; Sat, 27 May 2017 04:49:17 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="jY4T0ZOI"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=Jx2GZinIemxwksfA6wOjc48FDAiwamVBCPIvxivhMwXjfbyPNO p2GTxnmpxW2V3kaZur/X1PUL7YV9p/wgqzhALcD69EmPvQoV37E7vpjsRwpelcpx fHHduN0YB2wWiNBjdTh+kVCzgxBC/k8xlrNpiZLNLTzGfy2YWA/mM+4wU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=z8i6tMZUtz/1yhYKnNIDytMBgOE=; b=jY4T0ZOIcdliIiZLY5d6 1SrLGn++XWqq3BNPnSRSdPxEWcfA3F3nKJLkMKC3xYe04NcU0UV3nH7syA5QA3ks lPtxj0cGLA8aGhgoyrQOHidIeS+Q8v1Za3GNxYtsXSWJNPHSzdZTx/ICjlikZvWt A0Q2lSmIRoyjgRL5XKkMZ60= Received: (qmail 52579 invoked by alias); 26 May 2017 18:48:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47185 invoked by uid 89); 26 May 2017 18:48:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=wikipedia, Hx-languages-length:2046 X-HELO: smtp.ispras.ru Received: from bran.ispras.ru (HELO smtp.ispras.ru) (83.149.199.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 26 May 2017 18:48:46 +0000 Received: from monopod.intra.ispras.ru (monopod.intra.ispras.ru [10.10.3.121]) by smtp.ispras.ru (Postfix) with ESMTP id CFB7A5FC2A; Fri, 26 May 2017 21:48:46 +0300 (MSK) Date: Fri, 26 May 2017 21:48:46 +0300 (MSK) From: Alexander Monakov To: gcc-patches@gcc.gnu.org cc: Sandra Loosemore , Jan Hubicka Subject: [PATCH doc] update documentation of x86 -mcx16 option Message-ID: User-Agent: Alpine 2.20.13 (LNX 116 2015-12-14) MIME-Version: 1.0 Hi, This patch fixes a few issues in documentation of -mcx16 x86 backend option: - remove implementor-speak ('oword') - mention alignment restriction and availability only in 64-bit mode - improve usage example existing documentation uses a really silly example (128-bit integer counters), it was apparently taken from Wikipedia back in 2007; today, Wikipedia uses a far more realistic example ("This is useful for parallel algorithms that use compare and swap on data larger than the size of a pointer, common in lock-free and wait-free algorithms") - mention that the instruction is used when expanding __sync builtins, and NOT used when expanding __atomic builtins. This is a quiet change in GCC-7, GCC-6 and earlier used this instruction for __atomic builtins too. OK for trunk? For the gcc-7 branch? Thanks. Alexander * doc/invoke.texi (mcx16): Rewrite. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3308b63..0b3c296 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -25160,13 +25160,12 @@ This option instructs GCC to use 128-bit AVX instructions instead of @item -mcx16 @opindex mcx16 -This option enables GCC to generate @code{CMPXCHG16B} instructions. -@code{CMPXCHG16B} allows for atomic operations on 128-bit double quadword -(or oword) data types. -This is useful for high-resolution counters that can be updated -by multiple processors (or cores). This instruction is generated as part of -atomic built-in functions: see @ref{__sync Builtins} or -@ref{__atomic Builtins} for details. +This option enables GCC to generate @code{CMPXCHG16B} instructions in 64-bit +code to implement compare-and-exchange operations on 16-byte aligned 128-bit +objects. This is useful for atomic updates of data structures exceeding one +machine word in size. The compiler uses this instruction to implement +@ref{__sync Builtins}. However, for @ref{__atomic Builtins} operating on +128-bit integers, a library call is always used. @item -msahf @opindex msahf