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[wwwdocs] gcc-4.8/changes.html: mention IRA and transactional memory

Message ID alpine.LNX.2.00.1311260155320.1711@tuna.site
State New
Headers show

Commit Message

Gerald Pfeifer Nov. 26, 2013, 3:21 a.m. UTC 
On Mon, 20 May 2013, Aldy Hernandez wrote:
> I am committing the attached patch.

Thanks, Aldy.

I just noticed the casing of SPARC and a bit of an inconsistency
around IA-32, and committed the follow-up below (which also contains
one "back end" fix).

Gerald
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Patch

Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.8/changes.html,v
retrieving revision 1.123
diff -u -3 -p -r1.123 changes.html
--- changes.html	16 Oct 2013 13:47:15 -0000	1.123
+++ changes.html	26 Nov 2013 03:09:31 -0000
@@ -145,11 +145,11 @@  by this change.</p>
 	GNU/Linux.</li>
     <li>A new local register allocator (LRA) has been implemented, which
         replaces the 26 year old reload pass and improves generated
-        code quality.  For now it is active on the ia32 and x86-64
+        code quality.  For now it is active on the IA-32 and x86-64
         targets.</li>
     <li>Support for transactional memory has been implemented on the
         following architectures: IA-32/x86-64, ARM, PowerPC, SH,
-        Sparc, and Alpha.</li>
+        SPARC, and Alpha.</li>
   </ul>
 
 
@@ -639,7 +639,7 @@  int i = A().f();  // error, f() requires
     <a href="http://gcc.gnu.org/wiki/FunctionMultiVersioning">wiki</a> for more
     information.
     </li>
-    <li> The x86 backend has been improved to allow option
+    <li> The x86 back end has been improved to allow option
     <code>-fschedule-insns</code> to work reliably.
     This option can be used to schedule instructions better and leads to
     improved performace in certain cases.</li>