Message ID | alpine.LFD.2.21.2011200256200.656242@eddie.linux-mips.org |
---|---|
State | Accepted |
Headers | show |
Series | VAX: Bring the port up to date (yes, MODE_CC conversion is included) | expand |
On 11/19/20 8:35 PM, Maciej W. Rozycki wrote: > With the `*insv_aligned', `*extzv_aligned' and `*extv_aligned' insns we > are going to adjust the bitfield location if it is in memory, so only > allow such location addresses that can be offset, excluding external > symbol references in the PIC mode in particular. > > This fixes an ICE like: > > during RTL pass: final > In file included from .../gcc/testsuite/gcc.dg/torture/vshuf-v16qi.c:11: > .../gcc/testsuite/gcc.dg/torture/vshuf-main.inc: In function 'test_13': > .../gcc/testsuite/gcc.dg/torture/vshuf-main.inc:27:1: internal compiler error: in change_address_1, at emit-rtl.c:2275 > .../gcc/testsuite/gcc.dg/torture/vshuf-16.inc:16:1: note: in expansion of macro 'T' > .../gcc/testsuite/gcc.dg/torture/vshuf-main.inc:28:1: note: in expansion of macro 'TESTS' > 0x10a34b33 change_address_1 > .../gcc/emit-rtl.c:2275 > 0x10a358af adjust_address_1(rtx_def*, machine_mode, poly_int<1u, long>, int, int, int, poly_int<1u, long>) > .../gcc/emit-rtl.c:2409 > 0x11d2505f output_97 > .../gcc/config/vax/vax.md:806 > 0x10adec4b get_insn_template(int, rtx_insn*) > .../gcc/final.c:2070 > 0x10ae1c5b final_scan_insn_1 > .../gcc/final.c:3039 > 0x10ae2257 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*) > .../gcc/final.c:3152 > 0x10ade9a3 final_1 > .../gcc/final.c:2020 > 0x10ae6157 rest_of_handle_final > .../gcc/final.c:4658 > 0x10ae6697 execute > .../gcc/final.c:4736 > Please submit a full bug report, > with preprocessed source if appropriate. > Please include the complete backtrace with any bug report. > See <https://gcc.gnu.org/bugs/> for instructions. > compiler exited with status 1 > FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (internal compiler error) > > triggered by an RTL instruction like: > > (insn 97 96 98 (set (reg:SI 5 %r5 [88]) > (zero_extract:SI (mem/c:SI (symbol_ref:SI ("b") <var_decl 0x7ffff7f801b0 b>) [0 b+0 S4 A128]) > (const_int 8 [0x8]) > (const_int 24 [0x18]))) ".../gcc/testsuite/gcc.dg/torture/vshuf-main.inc":28:1 97 {*extzv_aligned} > (nil)) > > and removes these regressions: > > FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (test for excess errors) > FAIL: gcc.dg/torture/vshuf-v4hi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v4hi.c -O2 (test for excess errors) > FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 (test for excess errors) > FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 (test for excess errors) > > However expand typically presents pseudo-registers rather than memory > references to these insns, so a further rework is required to make a > better use of the code variant they are supposed to produce. This at > least fixes the problem at hand. > > gcc/ > * config/vax/vax.md (*insv_aligned, *extzv_aligned) > (*extv_aligned): Also make sure the memory address of a bitfield > location can be adjusted in the PIC mode. OK jeff
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md index 80f09d97727..f90ae89391f 100644 --- a/gcc/config/vax/vax.md +++ b/gcc/config/vax/vax.md @@ -762,11 +762,14 @@ (define_insn "*insv_aligned" (match_operand:QI 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 3 "general_operand" "g"))] - "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) + "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 && (!MEM_P (operands[0]) - || ! mode_dependent_address_p (XEXP (operands[0], 0), - MEM_ADDR_SPACE (operands[0]))) + || ((!flag_pic + || vax_acceptable_pic_operand_p (XEXP (operands[0], 0), + true, true)) + && !mode_dependent_address_p (XEXP (operands[0], 0), + MEM_ADDR_SPACE (operands[0])))) && (!(REG_P (operands[0]) || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0])))) || INTVAL (operands[2]) == 0)" @@ -794,8 +797,11 @@ (define_insn "*extzv_aligned" "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 && (!MEM_P (operands[1]) - || ! mode_dependent_address_p (XEXP (operands[1], 0), - MEM_ADDR_SPACE (operands[1]))) + || ((!flag_pic + || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), + true, true)) + && !mode_dependent_address_p (XEXP (operands[1], 0), + MEM_ADDR_SPACE (operands[1])))) && (!(REG_P (operands[1]) || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) || INTVAL (operands[3]) == 0)" @@ -822,8 +828,11 @@ (define_insn "*extv_aligned" "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 && (!MEM_P (operands[1]) - || ! mode_dependent_address_p (XEXP (operands[1], 0), - MEM_ADDR_SPACE (operands[1]))) + || ((!flag_pic + || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), + true, true)) + && !mode_dependent_address_p (XEXP (operands[1], 0), + MEM_ADDR_SPACE (operands[1])))) && (!(REG_P (operands[1]) || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) || INTVAL (operands[3]) == 0)"