@@ -10,7 +10,7 @@
sleu:
sgtu a0,a0,a1
xori a0,a0,1
- sext.w a0,a0
+ andi a0,a0,1
ret
.size sleu, .-sleu
.section .note.GNU-stack,"",@progbits
following Kito's observations. Which is why the tests incorrectly pass at
some optimisation levels while code produced is still suboptimal and just
trivially different.
> The key difference is Roger's patch:
>
> commit c23a9c87cc62bd177fd0d4db6ad34b34e1b9a31f
> Author: Roger Sayle <roger@nextmovesoftware.com>
> Date: Wed Aug 3 08:55:35 2022 +0100
>
> Some additional zero-extension related optimizations in simplify-rtx.
>
> This patch implements some additional zero-extension and sign-extension
> related optimizations in simplify-rtx.cc. The original motivation comes
> from PR rtl-optimization/71775, where in comment #2 Andrew Pinksi sees:
>
> Failed to match this instruction:
> (set (reg:DI 88 [ _1 ])
> (sign_extend:DI (subreg:SI (ctz:DI (reg/v:DI 86 [ x ])) 0)))
>
> [ ... ]
>
> With that patch the sign extension is removed and instead we generate the AND
> with 0x1.
>
> Old, from combine dump:
>
> Successfully matched this instruction:
> (set (reg/i:DI 10 a0)
> ! (sign_extend:DI (reg:SI 78)))
>
>
> New, from combine dump:
>
> (set (reg/i:DI 10 a0)
> ! (and:DI (subreg:DI (reg:SI 78) 0)
> ! (const_int 1 [0x1])))
>
> Note the date on Roger's patch, roughly the same time as yours. I suspect Kito
> had tested the truck with Roger's patch.
That indeed seems like the correct explanation. Thanks for tracking it
down!
> Your patch is probably still useful. I think Kito's only concern was to make
> sure we don't have the ANDI instruction in addition to not having the SEXT
> instruction. So still approved for trunk, just update the testcases to make
> sure we don't have the ANDI too.
Given the false negatives how about getting a bit stricter and also
checking there's nothing following the XORI instruction, like here?
It might be an overkill to have a check both for the sequence and for the
absence of ANDI or SEXT.W as well, but I'd rather have them both out of an
abundance of caution.
Maciej
Changes from v1:
- Update test cases so as to verify there's no extra operation between
XORI and the final RET, and that an ANDI instruction is not present
either.
- Update the change description to reflect changes in code generation.
---
gcc/config/riscv/riscv.cc | 4 ++--
gcc/testsuite/gcc.target/riscv/sge.c | 12 ++++++++++++
gcc/testsuite/gcc.target/riscv/sgeu.c | 12 ++++++++++++
gcc/testsuite/gcc.target/riscv/sle.c | 12 ++++++++++++
gcc/testsuite/gcc.target/riscv/sleu.c | 12 ++++++++++++
5 files changed, 50 insertions(+), 2 deletions(-)
gcc-riscv-int-order-inv-seqz.diff
===================================================================
@@ -3004,9 +3004,9 @@ riscv_emit_int_order_test (enum rtx_code
}
else if (invert_ptr == 0)
{
- rtx inv_target = riscv_force_binary (GET_MODE (target),
+ rtx inv_target = riscv_force_binary (word_mode,
inv_code, cmp0, cmp1);
- riscv_emit_binary (XOR, target, inv_target, const1_rtx);
+ riscv_emit_binary (EQ, target, inv_target, const0_rtx);
}
else
{
===================================================================
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int
+sge (int x, int y)
+{
+ return x >= y;
+}
+
+/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler-not "andi|sext\\.w" } } */
===================================================================
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int
+sgeu (unsigned int x, unsigned int y)
+{
+ return x >= y;
+}
+
+/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler-not "andi|sext\\.w" } } */
===================================================================
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int
+sle (int x, int y)
+{
+ return x <= y;
+}
+
+/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler-not "andi|sext\\.w" } } */
===================================================================
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int
+sleu (unsigned int x, unsigned int y)
+{
+ return x <= y;
+}
+
+/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler-not "andi|sext\\.w" } } */