| Message ID | alpine.DEB.2.20.2201272159420.11348@tpp.orcam.me.uk |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Document `auipc' and `bitmanip' `type' attributes | expand |
LGTM, thanks for correcting this oversight in my patch. On Thu, Jan 27, 2022 at 2:09 PM Maciej W. Rozycki <macro@embecosm.com> wrote: > > Document new `auipc' and `bitmanip' `type' attributes added respectively > with commit 88108b27dda9 ("RISC-V: Add sifive-7 pipeline description.") > and commit 283b1707f237 ("RISC-V: Implement instruction patterns for ZBA > extension.") but not listed so far. > > gcc/ > * config/riscv/riscv.md: Document `auipc' and `bitmanip' `type' > attributes. > --- > Hi, > > There's also the `rotate' `type' attribute, but it's nowhere used, so it > might be worth removing. As not-a-regression however that would be GCC 13 > material I guess. > > OK to apply? > > Maciej > --- > gcc/config/riscv/riscv.md | 2 ++ > 1 file changed, 2 insertions(+) > > gcc-riscv-auipc-bitmanip-type.diff > Index: gcc/gcc/config/riscv/riscv.md > =================================================================== > --- gcc.orig/gcc/config/riscv/riscv.md > +++ gcc/gcc/config/riscv/riscv.md > @@ -150,6 +150,7 @@ > ;; mfc transfer from coprocessor > ;; const load constant > ;; arith integer arithmetic instructions > +;; auipc integer addition to PC > ;; logical integer logical instructions > ;; shift integer shift instructions > ;; slt set less than instructions > @@ -167,6 +168,7 @@ > ;; multi multiword sequence (or user asm statements) > ;; nop no operation > ;; ghost an instruction that produces no real code > +;; bitmanip bit manipulation instructions > (define_attr "type" > "unknown,branch,jump,call,load,fpload,store,fpstore, > mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
On Thu, 27 Jan 2022, Andrew Waterman wrote:
> LGTM, thanks for correcting this oversight in my patch.
Committed, thanks for your review!
Maciej
Index: gcc/gcc/config/riscv/riscv.md =================================================================== --- gcc.orig/gcc/config/riscv/riscv.md +++ gcc/gcc/config/riscv/riscv.md @@ -150,6 +150,7 @@ ;; mfc transfer from coprocessor ;; const load constant ;; arith integer arithmetic instructions +;; auipc integer addition to PC ;; logical integer logical instructions ;; shift integer shift instructions ;; slt set less than instructions @@ -167,6 +168,7 @@ ;; multi multiword sequence (or user asm statements) ;; nop no operation ;; ghost an instruction that produces no real code +;; bitmanip bit manipulation instructions (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
Document new `auipc' and `bitmanip' `type' attributes added respectively with commit 88108b27dda9 ("RISC-V: Add sifive-7 pipeline description.") and commit 283b1707f237 ("RISC-V: Implement instruction patterns for ZBA extension.") but not listed so far. gcc/ * config/riscv/riscv.md: Document `auipc' and `bitmanip' `type' attributes. --- Hi, There's also the `rotate' `type' attribute, but it's nowhere used, so it might be worth removing. As not-a-regression however that would be GCC 13 material I guess. OK to apply? Maciej --- gcc/config/riscv/riscv.md | 2 ++ 1 file changed, 2 insertions(+) gcc-riscv-auipc-bitmanip-type.diff