From patchwork Thu Sep 1 21:32:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 665027 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sQFqw3q6Bz9s5w for ; Fri, 2 Sep 2016 07:33:48 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=mGF8nf22; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=m6cc4b+2CkBYG3HGHDF O6Dluroq1EPpPdpb+D1KNTIJRilWsWdenU9ZC7oi4GhOHk/CJAuUPRoB9+weDFa+ /qEHoHmE1CzfFhlCR06QUrYuOS3zIuAA/A+yR2J9k7DAiS6d3YN7y2YNj8Z+E3/T YQ0xGP7TBk7TZqFvYRj54s+c= DKIM-Signature: v=1; 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Thu, 01 Sep 2016 21:33:23 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 9250D1C06F6; Thu, 1 Sep 2016 21:33:22 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 2/4] rs6000: Rename 74 -> CR6_REGNO Date: Thu, 1 Sep 2016 21:32:04 +0000 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes 2016-09-01 Segher Boessenkool * config/rs6000/altivec.md: Use CR6_REGNO instead of 74 throughout. * config/rs6000/vector.md: Ditto. * config/rs6000/vsx.md: Ditto. --- gcc/config/rs6000/altivec.md | 30 +++++++++++++++--------------- gcc/config/rs6000/vector.md | 16 ++++++++-------- gcc/config/rs6000/vsx.md | 6 +++--- 3 files changed, 26 insertions(+), 26 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 25472c29..480e64e 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2274,7 +2274,7 @@ (define_insn "altivec_vupklpx" ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*altivec_vcmpequ_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2286,7 +2286,7 @@ (define_insn "*altivec_vcmpequ_p" [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgts_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2298,7 +2298,7 @@ (define_insn "*altivec_vcmpgts_p" [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgtu_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2310,7 +2310,7 @@ (define_insn "*altivec_vcmpgtu_p" [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpeqfp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2322,7 +2322,7 @@ (define_insn "*altivec_vcmpeqfp_p" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgtfp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2334,7 +2334,7 @@ (define_insn "*altivec_vcmpgtfp_p" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgefp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2346,7 +2346,7 @@ (define_insn "*altivec_vcmpgefp_p" [(set_attr "type" "veccmp")]) (define_insn "altivec_vcmpbfp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VCMPBFP)) @@ -3634,7 +3634,7 @@ (define_insn "bcd" (match_operand:V1TI 2 "register_operand" "") (match_operand:QI 3 "const_0_to_1_operand" "")] UNSPEC_BCD_ADD_SUB)) - (clobber (reg:CCFP 74))] + (clobber (reg:CCFP CR6_REGNO))] "TARGET_P8_VECTOR" "bcd. %0,%1,%2,%3" [(set_attr "length" "4") @@ -3646,7 +3646,7 @@ (define_insn "bcd" ;; probably should be one that can go in the VMX (Altivec) registers, so we ;; can't use DDmode or DFmode. (define_insn "*bcd_test" - [(set (reg:CCFP 74) + [(set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v") (match_operand:V1TI 2 "register_operand" "v") @@ -3665,7 +3665,7 @@ (define_insn "*bcd_test2" (match_operand:V1TI 2 "register_operand" "v") (match_operand:QI 3 "const_0_to_1_operand" "i")] UNSPEC_BCD_ADD_SUB)) - (set (reg:CCFP 74) + (set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_dup 1) (match_dup 2) @@ -3699,7 +3699,7 @@ (define_insn "darn" [(set_attr "type" "integer")]) (define_expand "bcd_" - [(parallel [(set (reg:CCFP 74) + [(parallel [(set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "") (match_operand:V1TI 2 "register_operand" "") @@ -3708,7 +3708,7 @@ (define_expand "bcd_" (match_dup 4))) (clobber (match_scratch:V1TI 5 ""))]) (set (match_operand:SI 0 "register_operand" "") - (BCD_TEST:SI (reg:CCFP 74) + (BCD_TEST:SI (reg:CCFP CR6_REGNO) (const_int 0)))] "TARGET_P8_VECTOR" { @@ -3727,8 +3727,8 @@ (define_peephole2 (match_operand:V1TI 2 "register_operand" "") (match_operand:QI 3 "const_0_to_1_operand" "")] UNSPEC_BCD_ADD_SUB)) - (clobber (reg:CCFP 74))]) - (parallel [(set (reg:CCFP 74) + (clobber (reg:CCFP CR6_REGNO))]) + (parallel [(set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_dup 1) (match_dup 2) @@ -3742,7 +3742,7 @@ (define_peephole2 (match_dup 2) (match_dup 3)] UNSPEC_BCD_ADD_SUB)) - (set (reg:CCFP 74) + (set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_dup 1) (match_dup 2) diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index fbfa9bf..d42de0f 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -670,7 +670,7 @@ (define_expand "vector_select__uns" ;; setting CR6 to indicate a combined status (define_expand "vector_eq__p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "") (match_operand:VEC_A 2 "vlogical_operand" ""))] UNSPEC_PREDICATE)) @@ -682,7 +682,7 @@ (define_expand "vector_eq__p" (define_expand "vector_gt__p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "") (match_operand:VEC_A 2 "vlogical_operand" ""))] UNSPEC_PREDICATE)) @@ -694,7 +694,7 @@ (define_expand "vector_gt__p" (define_expand "vector_ge__p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "") (match_operand:VEC_F 2 "vfloat_operand" ""))] UNSPEC_PREDICATE)) @@ -706,7 +706,7 @@ (define_expand "vector_ge__p" (define_expand "vector_gtu__p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" ""))] UNSPEC_PREDICATE)) @@ -720,14 +720,14 @@ (define_expand "vector_gtu__p" (define_expand "cr6_test_for_zero" [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (reg:CC 74) + (eq:SI (reg:CC CR6_REGNO) (const_int 0)))] "TARGET_ALTIVEC || TARGET_VSX" "") (define_expand "cr6_test_for_zero_reverse" [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (reg:CC 74) + (eq:SI (reg:CC CR6_REGNO) (const_int 0))) (set (match_dup 0) (xor:SI (match_dup 0) @@ -737,14 +737,14 @@ (define_expand "cr6_test_for_zero_reverse" (define_expand "cr6_test_for_lt" [(set (match_operand:SI 0 "register_operand" "=r") - (lt:SI (reg:CC 74) + (lt:SI (reg:CC CR6_REGNO) (const_int 0)))] "TARGET_ALTIVEC || TARGET_VSX" "") (define_expand "cr6_test_for_lt_reverse" [(set (match_operand:SI 0 "register_operand" "=r") - (lt:SI (reg:CC 74) + (lt:SI (reg:CC CR6_REGNO) (const_int 0))) (set (match_dup 0) (xor:SI (match_dup 0) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 60917c5..359e424 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1499,7 +1499,7 @@ (define_insn "*vsx_ge" ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*vsx_eq__p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?") (match_operand:VSX_F 2 "vsx_register_operand" ",?"))] @@ -1512,7 +1512,7 @@ (define_insn "*vsx_eq__p" [(set_attr "type" "")]) (define_insn "*vsx_gt__p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?") (match_operand:VSX_F 2 "vsx_register_operand" ",?"))] @@ -1525,7 +1525,7 @@ (define_insn "*vsx_gt__p" [(set_attr "type" "")]) (define_insn "*vsx_ge__p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?") (match_operand:VSX_F 2 "vsx_register_operand" ",?"))]