@@ -460,8 +460,6 @@ (define_code_attr return_str [(return "") (simple_return "simple_")])
; Logical operators.
(define_code_iterator iorxor [ior xor])
-(define_code_attr iorxor [(ior "ior") (xor "xor")])
-(define_code_attr IORXOR [(ior "IOR") (xor "XOR")])
; Signed/unsigned variants of ops.
(define_code_iterator any_extend [sign_extend zero_extend])
@@ -2876,7 +2874,7 @@ (define_insn_and_split "*andsi3_internal6"
[(set_attr "length" "8")])
-(define_expand "<iorxor><mode>3"
+(define_expand "<code><mode>3"
[(set (match_operand:SDI 0 "gpc_reg_operand" "")
(iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
(match_operand:SDI 2 "reg_or_cint_operand" "")))]
@@ -2884,7 +2882,7 @@ (define_expand "<iorxor><mode>3"
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
{
- rs6000_split_logical (operands, <IORXOR>, false, false, false);
+ rs6000_split_logical (operands, <CODE>, false, false, false);
DONE;
}
@@ -2898,8 +2896,8 @@ (define_expand "<iorxor><mode>3"
HOST_WIDE_INT lo = value & 0xffff;
HOST_WIDE_INT hi = value - lo;
- emit_insn (gen_<iorxor><mode>3 (tmp, operands[1], GEN_INT (hi)));
- emit_insn (gen_<iorxor><mode>3 (operands[0], tmp, GEN_INT (lo)));
+ emit_insn (gen_<code><mode>3 (tmp, operands[1], GEN_INT (hi)));
+ emit_insn (gen_<code><mode>3 (operands[0], tmp, GEN_INT (lo)));
DONE;
}