Message ID | a62eb606-01e4-4617-abf5-7010f03b207c@gmail.com |
---|---|
State | New |
Headers | show |
Series | RISC-V: Do not allow v0 as dest when merging [PR115068]. | expand |
Hi, Robin.
I saw vwadd/vwsub.wx have same issue. Could you change them and add test too ?
Thanks.
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2024-05-14 04:15
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zhong@rivai.ai; jeffreyalaw
Subject: [PATCH] RISC-V: Do not allow v0 as dest when merging [PR115068].
Hi,
this patch splits the vfw...wf pattern so we do not emit
e.g. vfwadd.wf v0,v8,fa5,v0.t anymore.
Regtested on rv64gcv_zvfh.
Regards
Robin
gcc/ChangeLog:
PR target/115068
* config/riscv/vector.md: Split vfw<insn>.wf pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr115068-run.c: New test.
* gcc.target/riscv/rvv/base/pr115068.c: New test.
---
gcc/config/riscv/vector.md | 20 ++++++-------
.../gcc.target/riscv/rvv/base/pr115068-run.c | 28 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/pr115068.c | 29 +++++++++++++++++++
3 files changed, 67 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 2a54f78df8e..e408baa809c 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7178,24 +7178,24 @@ (define_insn "@pred_single_widen_sub<mode>"
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
- [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr")
+ [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vd, vr, vr")
(if_then_else:VWEXTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (match_operand 9 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VWEXTF
- (match_operand:VWEXTF 3 "register_operand" " vr, vr")
+ (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr")
(float_extend:VWEXTF
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f"))))
+ (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c
new file mode 100644
index 00000000000..95ec8e06021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-std=gnu99" } */
+
+#include <stdint.h>
+#include <riscv_vector.h>
+
+vfloat64m8_t
+test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl)
+{
+ return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl);
+}
+
+char global_memory[1024];
+void *fake_memory = (void *) global_memory;
+
+int
+main ()
+{
+ asm volatile ("fence" ::: "memory");
+ vfloat64m8_t vfwadd_wf_f64m8_m_vd = test_vfwadd_wf_f64m8_m (
+ __riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()),
+ __riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
+ asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory");
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
new file mode 100644
index 00000000000..6d680037aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-std=gnu99" } */
+
+#include <stdint.h>
+#include <riscv_vector.h>
+
+vfloat64m8_t
+test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl)
+{
+ return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl);
+}
+
+char global_memory[1024];
+void *fake_memory = (void *) global_memory;
+
+int
+main ()
+{
+ asm volatile ("fence" ::: "memory");
+ vfloat64m8_t vfwadd_wf_f64m8_m_vd = test_vfwadd_wf_f64m8_m (
+ __riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()),
+ __riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
+ asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory");
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not "vfwadd.wf\tv0.*v0" } } */
> I saw vwadd/vwsub.wx have same issue. Could you change them and add test too ?
Yes, will do. At first I didn't manage to reproduce it because we
seem to be lacking a combine-opt pattern for it. I'm going to post
it separately.
Regards
Robin
LGTM this patch (fix for vfwadd.wf). And here is a simpel case to reproduce same bug for vwadd.wx: https://compiler-explorer.com/z/4rP9Yvdq1 #include <stdint.h> #include <riscv_vector.h> vint64m8_t test_vwadd_wx_i64m8_m(vbool8_t vm, vint64m8_t vs2, int rs1, size_t vl) { return __riscv_vwadd_wx_i64m8_m(vm, vs2, rs1, vl); } char global_memory[1024]; void *fake_memory = (void *)global_memory; int main () { asm volatile("fence":::"memory"); long x; asm volatile("":"=r"(x)::"memory"); vint64m8_t vwadd_wx_i64m8_m_vd = test_vwadd_wx_i64m8_m( __riscv_vreinterpret_v_i8m1_b8(__riscv_vundefined_i8m1()), __riscv_vundefined_i64m8(), x, __riscv_vsetvlmax_e64m8()); asm volatile(""::"vr"(vwadd_wx_i64m8_m_vd):"memory"); return 0; } main: fence vsetvli a4,zero,e32,m4,ta,ma vwadd.wx v0,v8,a5,v0.t ----> vd and vm are both v0 which is wrong. li a0,0 ret juzhe.zhong@rivai.ai From: Robin Dapp Date: 2024-05-16 03:31 To: 钟居哲; gcc-patches CC: rdapp.gcc; palmer; kito.cheng; Jeff Law Subject: Re: [PATCH] RISC-V: Do not allow v0 as dest when merging [PR115068]. > I saw vwadd/vwsub.wx have same issue. Could you change them and add test too ? Yes, will do. At first I didn't manage to reproduce it because we seem to be lacking a combine-opt pattern for it. I'm going to post it separately. Regards Robin
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 2a54f78df8e..e408baa809c 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7178,24 +7178,24 @@ (define_insn "@pred_single_widen_sub<mode>" (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VWEXTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (match_operand 9 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 3 "register_operand" " vr, vr") + (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr") (float_extend:VWEXTF (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 4 "register_operand" " f, f")))) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] + (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f")))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfw<insn>.wf\t%0,%3,%4%p1" [(set_attr "type" "vf<widen_binop_insn_type>") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c new file mode 100644 index 00000000000..95ec8e06021 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-add-options riscv_v } */ +/* { dg-additional-options "-std=gnu99" } */ + +#include <stdint.h> +#include <riscv_vector.h> + +vfloat64m8_t +test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl) +{ + return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl); +} + +char global_memory[1024]; +void *fake_memory = (void *) global_memory; + +int +main () +{ + asm volatile ("fence" ::: "memory"); + vfloat64m8_t vfwadd_wf_f64m8_m_vd = test_vfwadd_wf_f64m8_m ( + __riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()), + __riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ()); + asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory"); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c new file mode 100644 index 00000000000..6d680037aa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-add-options riscv_v } */ +/* { dg-additional-options "-std=gnu99" } */ + +#include <stdint.h> +#include <riscv_vector.h> + +vfloat64m8_t +test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl) +{ + return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl); +} + +char global_memory[1024]; +void *fake_memory = (void *) global_memory; + +int +main () +{ + asm volatile ("fence" ::: "memory"); + vfloat64m8_t vfwadd_wf_f64m8_m_vd = test_vfwadd_wf_f64m8_m ( + __riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()), + __riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ()); + asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory"); + + return 0; +} + +/* { dg-final { scan-assembler-not "vfwadd.wf\tv0.*v0" } } */