| Message ID | ZVZajnB6xr3pQF3M@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | aarch64: Rework ldp/stp patterns, add new ldp/stp pass | expand |
Alex Coplan <alex.coplan@arm.com> writes: > For the ret function, allow the loads to be emitted in either order in > the codegen. The order gets inverted with the new load/store pair pass. > > OK for trunk? > > gcc/testsuite/ChangeLog: > > * g++.target/aarch64/pr103147-10.C (ret): Allow loads in either order. OK, but: would adding -fno-schedule-insns -fno-schedule-insns2 also have worked? It's usually a good idea to pass those options to -O2 check-function-bodies tests, if the test checks for insns that have dependency. In this case, those options would ensure that nothing else gets moved between the loads. So OK as-is, but also OK with the options instead. Thanks, Richard > * gcc.target/aarch64/pr103147-10.c (ret): Likewise. > --- > gcc/testsuite/g++.target/aarch64/pr103147-10.C | 5 +++++ > gcc/testsuite/gcc.target/aarch64/pr103147-10.c | 5 +++++ > 2 files changed, 10 insertions(+) > > diff --git a/gcc/testsuite/g++.target/aarch64/pr103147-10.C b/gcc/testsuite/g++.target/aarch64/pr103147-10.C > index e12771533f7..5a98c30ed3f 100644 > --- a/gcc/testsuite/g++.target/aarch64/pr103147-10.C > +++ b/gcc/testsuite/g++.target/aarch64/pr103147-10.C > @@ -62,8 +62,13 @@ ld4 (int32x4x4_t *a, int32_t *b) > /* > ** ret: > ** ... > +** ( > ** ldp q0, q1, \[x0\] > ** ldr q2, \[x0, #?32\] > +** | > +** ldr q2, \[x0, #?32\] > +** ldp q0, q1, \[x0\] > +** ) > ** ... > */ > int32x4x3_t > diff --git a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c > index 57942bfd10a..2609266bc46 100644 > --- a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c > +++ b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c > @@ -60,8 +60,13 @@ ld4 (int32x4x4_t *a, int32_t *b) > /* > ** ret: > ** ... > +** ( > ** ldp q0, q1, \[x0\] > ** ldr q2, \[x0, #?32\] > +** | > +** ldr q2, \[x0, #?32\] > +** ldp q0, q1, \[x0\] > +** ) > ** ... > */ > int32x4x3_t
diff --git a/gcc/testsuite/g++.target/aarch64/pr103147-10.C b/gcc/testsuite/g++.target/aarch64/pr103147-10.C index e12771533f7..5a98c30ed3f 100644 --- a/gcc/testsuite/g++.target/aarch64/pr103147-10.C +++ b/gcc/testsuite/g++.target/aarch64/pr103147-10.C @@ -62,8 +62,13 @@ ld4 (int32x4x4_t *a, int32_t *b) /* ** ret: ** ... +** ( ** ldp q0, q1, \[x0\] ** ldr q2, \[x0, #?32\] +** | +** ldr q2, \[x0, #?32\] +** ldp q0, q1, \[x0\] +** ) ** ... */ int32x4x3_t diff --git a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c index 57942bfd10a..2609266bc46 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c +++ b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c @@ -60,8 +60,13 @@ ld4 (int32x4x4_t *a, int32_t *b) /* ** ret: ** ... +** ( ** ldp q0, q1, \[x0\] ** ldr q2, \[x0, #?32\] +** | +** ldr q2, \[x0, #?32\] +** ldp q0, q1, \[x0\] +** ) ** ... */ int32x4x3_t