| Message ID | ZS7zS9xTDJNnjpQl@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | aarch64: Add new load/store pair fusion pass | expand |
Alex Coplan <alex.coplan@arm.com> writes: > With the new ldp/stp pass enabled, there is a change in the codegen for > this test as follows: > > add x8, sp, 16 > ptrue p3.h, mul3 > str p3, [x8] > - str x8, [sp, 8] > - str x9, [sp] > + stp x9, x8, [sp] > ptrue p3.d, vl8 > ptrue p2.s, vl7 > ptrue p1.h, vl6 > > i.e. we now form an stp that we were missing previously. This patch > adjusts the scan-assembler such that it should pass whether or not > we form the stp. > > Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk? > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/sve/pcs/args_9.c: Adjust scan-assemblers to > allow for stp. OK, thanks. Richard > --- > gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c > index ad9affadf02..942a44ab448 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c > @@ -45,5 +45,5 @@ caller (int64_t *x0, int16_t *x1, svbool_t p0) > return svcntp_b8 (res, res); > } > > -/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.b, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\tstr\t\2, \[sp\]\n} } } */ > -/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.h, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\tstr\t\2, \[sp, 8\]\n} } } */ > +/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.b, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\t(?:str\t\2, \[sp\]|stp\t\2, x[0-9]+, \[sp\])\n} } } */ > +/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.h, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\t(?:str\t\2, \[sp, 8\]|stp\tx[0-9]+, \2, \[sp\])\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c index ad9affadf02..942a44ab448 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c @@ -45,5 +45,5 @@ caller (int64_t *x0, int16_t *x1, svbool_t p0) return svcntp_b8 (res, res); } -/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.b, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\tstr\t\2, \[sp\]\n} } } */ -/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.h, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\tstr\t\2, \[sp, 8\]\n} } } */ +/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.b, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\t(?:str\t\2, \[sp\]|stp\t\2, x[0-9]+, \[sp\])\n} } } */ +/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.h, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\t(?:str\t\2, \[sp, 8\]|stp\tx[0-9]+, \2, \[sp\])\n} } } */
With the new ldp/stp pass enabled, there is a change in the codegen for this test as follows: add x8, sp, 16 ptrue p3.h, mul3 str p3, [x8] - str x8, [sp, 8] - str x9, [sp] + stp x9, x8, [sp] ptrue p3.d, vl8 ptrue p2.s, vl7 ptrue p1.h, vl6 i.e. we now form an stp that we were missing previously. This patch adjusts the scan-assembler such that it should pass whether or not we form the stp. Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk? gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/pcs/args_9.c: Adjust scan-assemblers to allow for stp. --- gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)