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Thu, 12 Nov 2020 19:34:57 +0000 To: GCC Patches Subject: [3/3][aarch64] Add support for vec_widen_shift pattern Thread-Topic: [3/3][aarch64] Add support for vec_widen_shift pattern Thread-Index: AQHWuQXC73lz0vPpdkaYS7MmzBpCdA== Date: Thu, 12 Nov 2020 19:34:57 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Authentication-Results-Original: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; x-originating-ip: [217.140.99.251] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: cbdce3e0-5ae7-4e6f-f946-08d887420ec2 x-ms-traffictypediagnostic: DB6PR0802MB2200:|VI1PR08MB4030: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:3826;OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: +CrVrYEXKUNMxcv/W06o0tQ2BDSG87Jize7ppzG8esQsseVSPsiU/02Hw7i86jYr5+Wlr08H/KEWzMXXPkFnylH0p9D/rWp7ZWUAe+HlQizBbXmI+YV5R/YiyFGsHIYTgY11yKwvnzaRiwMefqFGcOu0kudKUi6hamjeIhztoUxg8StDOCu4Cj9wriSmb+3wvBXrzhzhNiWXJXdvul0B2V/F8evpQ6wFva9sWq8miCz8U/GIS5zydjBVVa1fhf7l4cEmSMcD3g56O9RT6VlYjrXFOGXlSoNpY1u/BZLUIOfW9muIx4TdzAQcb/WYZ9EOk7ylSBQerIzZed4m5ncjaQ== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; 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DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2020 19:35:05.7435 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbdce3e0-5ae7-4e6f-f946-08d887420ec2 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB4030 X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Joel Hutton via Gcc-patches From: Joel Hutton Reply-To: Joel Hutton Cc: Richard Biener Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi all, This patch adds support in the aarch64 backend for the vec_widen_shift vect-pattern and makes a minor mid-end fix to support it. All 3 patches together bootstrapped and regression tested on aarch64. Ok for stage 1? gcc/ChangeLog: 2020-11-12  Joel Hutton           * config/aarch64/aarch64-simd.md: vec_widen_lshift_hi/lo patterns         * tree-vect-stmts.c         (vectorizable_conversion): Fix for widen_lshift case gcc/testsuite/ChangeLog: 2020-11-12  Joel Hutton           * gcc.target/aarch64/vect-widen-lshift.c: New test. From 97af35b2d2a505dcefd8474cbd4bc3441b83ab02 Mon Sep 17 00:00:00 2001 From: Joel Hutton Date: Thu, 12 Nov 2020 11:48:25 +0000 Subject: [PATCH 3/3] [AArch64][vect] vec_widen_lshift pattern Add aarch64 vec_widen_lshift_lo/hi patterns and fix bug it triggers in mid-end. --- gcc/config/aarch64/aarch64-simd.md | 66 +++++++++++++++++++ .../gcc.target/aarch64/vect-widen-lshift.c | 60 +++++++++++++++++ gcc/tree-vect-stmts.c | 9 ++- 3 files changed, 133 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-widen-lshift.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b4f56a2295926f027bd53e7456eec729af0cd6df..2bb39c530a1a861cb9bd3df0c2943f62bd6153d7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4711,8 +4711,74 @@ [(set_attr "type" "neon_sat_shift_reg")] ) +(define_expand "vec_widen_shiftl_lo_" + [(set (match_operand: 0 "register_operand" "=w") + (unspec: [(match_operand:VQW 1 "register_operand" "w") + (match_operand:SI 2 + "aarch64_simd_shift_imm_bitsize_" "i")] + VSHLL))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); + emit_insn (gen_aarch64_shll_internal (operands[0], operands[1], + p, operands[2])); + DONE; + } +) + +(define_expand "vec_widen_shiftl_hi_" + [(set (match_operand: 0 "register_operand") + (unspec: [(match_operand:VQW 1 "register_operand" "w") + (match_operand:SI 2 + "immediate_operand" "i")] + VSHLL))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); + emit_insn (gen_aarch64_shll2_internal (operands[0], operands[1], + p, operands[2])); + DONE; + } +) + ;; vshll_n +(define_insn "aarch64_shll_internal" + [(set (match_operand: 0 "register_operand" "=w") + (unspec: [(vec_select: + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 2 "vect_par_cnst_lo_half" "")) + (match_operand:SI 3 + "aarch64_simd_shift_imm_bitsize_" "i")] + VSHLL))] + "TARGET_SIMD" + { + if (INTVAL (operands[3]) == GET_MODE_UNIT_BITSIZE (mode)) + return "shll\\t%0., %1., %3"; + else + return "shll\\t%0., %1., %3"; + } + [(set_attr "type" "neon_shift_imm_long")] +) + +(define_insn "aarch64_shll2_internal" + [(set (match_operand: 0 "register_operand" "=w") + (unspec: [(vec_select: + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 2 "vect_par_cnst_hi_half" "")) + (match_operand:SI 3 + "aarch64_simd_shift_imm_bitsize_" "i")] + VSHLL))] + "TARGET_SIMD" + { + if (INTVAL (operands[3]) == GET_MODE_UNIT_BITSIZE (mode)) + return "shll2\\t%0., %1., %3"; + else + return "shll2\\t%0., %1., %3"; + } + [(set_attr "type" "neon_shift_imm_long")] +) + (define_insn "aarch64_shll_n" [(set (match_operand: 0 "register_operand" "=w") (unspec: [(match_operand:VD_BHSI 1 "register_operand" "w") diff --git a/gcc/testsuite/gcc.target/aarch64/vect-widen-lshift.c b/gcc/testsuite/gcc.target/aarch64/vect-widen-lshift.c new file mode 100644 index 0000000000000000000000000000000000000000..23ed93d1dcbc3ca559efa6708b4ed5855fb6a050 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-widen-lshift.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -save-temps" } */ +#include +#include + +#define ARR_SIZE 1024 + +/* Should produce an shll,shll2 pair*/ +void sshll_opt (int32_t *foo, int16_t *a, int16_t *b) +{ + for( int i = 0; i < ARR_SIZE - 3;i=i+4) + { + foo[i] = a[i] << 16; + foo[i+1] = a[i+1] << 16; + foo[i+2] = a[i+2] << 16; + foo[i+3] = a[i+3] << 16; + } +} + +__attribute__((optimize (0))) +void sshll_nonopt (int32_t *foo, int16_t *a, int16_t *b) +{ + for( int i = 0; i < ARR_SIZE - 3;i=i+4) + { + foo[i] = a[i] << 16; + foo[i+1] = a[i+1] << 16; + foo[i+2] = a[i+2] << 16; + foo[i+3] = a[i+3] << 16; + } +} + + +void __attribute__((optimize (0))) +init(uint16_t *a, uint16_t *b) +{ + for( int i = 0; i < ARR_SIZE;i++) + { + a[i] = i; + b[i] = 2*i; + } +} + +int __attribute__((optimize (0))) +main() +{ + uint32_t foo_arr[ARR_SIZE]; + uint32_t bar_arr[ARR_SIZE]; + uint16_t a[ARR_SIZE]; + uint16_t b[ARR_SIZE]; + + init(a, b); + sshll_opt(foo_arr, a, b); + sshll_nonopt(bar_arr, a, b); + if (memcmp(foo_arr, bar_arr, ARR_SIZE) != 0) + return 1; + return 0; +} + +/* { dg-final { scan-assembler-times "shll\t" 1} } */ +/* { dg-final { scan-assembler-times "shll2\t" 1} } */ diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c index f12fd158b13656ee24022ec7e445c53444be6554..1f40b59c0560eec675af1d9a0e3e818d47589de6 100644 --- a/gcc/tree-vect-stmts.c +++ b/gcc/tree-vect-stmts.c @@ -4934,8 +4934,13 @@ vectorizable_conversion (vec_info *vinfo, &vec_oprnds1); if (code == WIDEN_LSHIFT_EXPR) { - vec_oprnds1.create (ncopies * ninputs); - for (i = 0; i < ncopies * ninputs; ++i) + int oprnds_size = ncopies * ninputs; + /* In the case of SLP ncopies = 1, so the size of vec_oprnds1 here + * should be obtained by the the size of vec_oprnds0. */ + if (slp_node) + oprnds_size = vec_oprnds0.length (); + vec_oprnds1.create (oprnds_size); + for (i = 0; i < oprnds_size; ++i) vec_oprnds1.quick_push (op1); } /* Arguments are ready. Create the new vector stmts. */ -- 2.17.1