Message ID | VI1PR0801MB2127D02B3FBEC6272644563683430@VI1PR0801MB2127.eurprd08.prod.outlook.com |
---|---|
State | New |
Headers | show |
Series | [GCC8,AArch64] Backport Cortex-A76, Ares and Neoverse N1 cpu names | expand |
On 12/2/19 12:14 PM, Wilco Dijkstra wrote: > Add support for Cortex-A76, Ares and Neoverse N1 cpu names in GCC8 branch. > > 2019-11-29 Wilco Dijkstra <wdijkstr@arm.com> > > * config/aarch64/aarch64-cores.def (ares): Define. > (cortex-a76): Likewise. > (neoverse-n1): Likewise. > * config/aarch64/aarch64-tune.md: Regenerate. > * doc/invoke.texi (AArch64 Options): Document ares, cortex-a76 and > neoverse-n1. > Ok as it's very non-invasive and provides a convenience to users of that branch. Thanks, Kyrill > -- > diff --git a/gcc/config/aarch64/aarch64-cores.def > b/gcc/config/aarch64/aarch64-cores.def > index > 33b96ca2861dce506a854cff19cfcaa32f0db23a..f48b7c22b2d261203ac25c010a054e47c291ddfc > 100644 > --- a/gcc/config/aarch64/aarch64-cores.def > +++ b/gcc/config/aarch64/aarch64-cores.def > @@ -85,6 +85,9 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, > thunderx2t99, 8_1A, AARCH64_FL_FOR > /* ARM ('A') cores. */ > AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, > AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | > AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) > AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, > AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | > AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) > +AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, > AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | > AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) > +AARCH64_CORE("ares", ares, cortexa57, 8_2A, > AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | > AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0c, -1) > +AARCH64_CORE("neoverse-n1", neoversen1,cortexa57, 8_2A, > AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | > AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0c, -1) > > /* ARMv8.3-A Architecture Processors. */ > > diff --git a/gcc/config/aarch64/aarch64-tune.md > b/gcc/config/aarch64/aarch64-tune.md > index > 7b3a7460561ee87e13799f726919c3f870781f6d..f08b7e44b27beeb41df928cf3aa09e59e734b5d2 > 100644 > --- a/gcc/config/aarch64/aarch64-tune.md > +++ b/gcc/config/aarch64/aarch64-tune.md > @@ -1,5 +1,5 @@ > ;; -*- buffer-read-only: t -*- > ;; Generated automatically by gentune.sh from aarch64-cores.def > (define_attr "tune" > -"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" > +"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index > c63f5611afb52b2358207a458dd6c275403a5a45..57340cea31df315ce37cfd57e084844da78df9fe > 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -14747,6 +14747,7 @@ Specify the name of the target processor for > which GCC should tune the > performance of the code. Permissible values for this option are: > @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, > @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, > @samp{cortex-a75}, > +@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1} > @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira}, > @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, > @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 33b96ca2861dce506a854cff19cfcaa32f0db23a..f48b7c22b2d261203ac25c010a054e47c291ddfc 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -85,6 +85,9 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR /* ARM ('A') cores. */ AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) +AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) +AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0c, -1) +AARCH64_CORE("neoverse-n1", neoversen1,cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0c, -1) /* ARMv8.3-A Architecture Processors. */ diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 7b3a7460561ee87e13799f726919c3f870781f6d..f08b7e44b27beeb41df928cf3aa09e59e734b5d2 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c63f5611afb52b2358207a458dd6c275403a5a45..57340cea31df315ce37cfd57e084844da78df9fe 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14747,6 +14747,7 @@ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, +@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1} @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},