From patchwork Wed Jul 24 15:16:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 1136397 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-505612-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="rtKVoB3U"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="4/sBd2RR"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="4/sBd2RR"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45tzTK46fMz9s4Y for ; Thu, 25 Jul 2019 01:16:37 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=NHq 3xiN6ZULaHibmL+4LSvvi/NEXUAnOYauccBiHiciT9ELrcPo7F2VCkFdaizlSo2V e06xbRMhsUCGWzdcuZ2U/T6h96Pg5BWN6jzgEeAMUmtILR+WYsT1S7vXs8U9YH9t kDD6FGEnt4CBFrByEiFZnINtvNkZvKnZMJqrNAUk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=NxQ0I2D54 nFEIJi0sae85p/bMsM=; b=rtKVoB3U/83WeRgHHoZa320ejlRbpTIv5Dl+/Zu5V fVitR6XED6g1u0i3vkl/zNiBKwmprP2/e/LstSOfh9JR4QXpiOq8b4fyCoXOPIpF 4Ea4OoOI4rfvdCQZzX0oSInmGNZK9SRyjcPP5CehGOJzptn6lVVaim2mCxC4JaXn YE= Received: (qmail 112313 invoked by alias); 24 Jul 2019 15:16:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 112304 invoked by uid 89); 24 Jul 2019 15:16:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Spam-Relays-External:sk:VE1EUR0, H*RU:sk:VE1EUR0, expense X-HELO: EUR01-VE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr140042.outbound.protection.outlook.com (HELO EUR01-VE1-obe.outbound.protection.outlook.com) (40.107.14.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 24 Jul 2019 15:16:27 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p3M3evzh7nd0UM5kn7EQQBVzoLU/BADl28kKfwr+ruA=; b=4/sBd2RR+p2sPRaJn/973Lbq94kdvL2LvepLtXUV5e9iERYbOR8BNGglJBU4uEFhv8Cosycvc26iIYVMYdV6E88MNhURr0JHDDSf1SD3GChi3C+sPMKbUuUy9O+LbmcvGaYgDAt92Mml0xlKn1CAfpr2oDxYl7R9mHIvrlRHMTU= Received: from VI1PR08CA0180.eurprd08.prod.outlook.com (2603:10a6:800:d1::34) by HE1PR0802MB2602.eurprd08.prod.outlook.com (2603:10a6:3:e2::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2094.17; Wed, 24 Jul 2019 15:16:21 +0000 Received: from VE1EUR03FT006.eop-EUR03.prod.protection.outlook.com (2a01:111:f400:7e09::206) by VI1PR08CA0180.outlook.office365.com (2603:10a6:800:d1::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2094.14 via Frontend Transport; Wed, 24 Jul 2019 15:16:21 +0000 Authentication-Results: spf=temperror (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; gcc.gnu.org; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; gcc.gnu.org; dmarc=temperror action=none header.from=arm.com; Received-SPF: TempError (protection.outlook.com: error in processing during lookup of arm.com: DNS Timeout) Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VE1EUR03FT006.mail.protection.outlook.com (10.152.18.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2052.18 via Frontend Transport; Wed, 24 Jul 2019 15:16:19 +0000 Received: ("Tessian outbound cc8a947d4660:v26"); Wed, 24 Jul 2019 15:16:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 748af69fddfacb8f X-CR-MTA-TID: 64aa7808 Received: from bfa21f8362f3.2 (ip-172-16-0-2.eu-west-1.compute.internal [104.47.5.55]) by 64aa7808-outbound-1.mta.getcheckrecipient.com id F6B338B7-2E0D-45B3-991A-CCCFFD12D41C.1; Wed, 24 Jul 2019 15:16:14 +0000 Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-he1eur02lp2055.outbound.protection.outlook.com [104.47.5.55]) by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id bfa21f8362f3.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Wed, 24 Jul 2019 15:16:14 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iwUb/cctMraLWqlfiFN9gh5JVStgCLVkuvtYGoHM+fIQmocTcTKdyw5JiQrMtYmRiHHC144haxlFdU+s8GoMw85mmF+cunKsWtbpYTRpLsVzMXdRpeUWefL3Ob5voDotvGYH5w/Qlxw/oJoSr9C9O4hiT88P7lCOYp6kPY+n30VY+PIXENa2g9C+kMyrPfniGkIu9VKMYefisSovmJJ96gumGUKuwHO3yB/DItrqFehQekA/FgB/0lFJ65sRHXNfaljjmYduQgnT6UBjHK5hU8DgZ0kmkKZYYxE/L18NvbLag706Dc8dH9thKXXOTKjlWSVPTjd2bHOrA/djOw2BEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p3M3evzh7nd0UM5kn7EQQBVzoLU/BADl28kKfwr+ruA=; b=Xk9JhBfNpYELGFmG4w/Wz3wUyuOG9uBHkbADqpNps28aTVXQJ8aNvlXO+X0hEN+KhY+3Aqv3wLOF8gx+qJXnLpsAQL+tf5cN0xsH6t80vlfo1d0PyOsSDg8Gtxe6aaY5z+xMZKJghkZIQL+qUC+CENM5h/mVIFsGYfG7m78+FLaBEvC4aBsS5C0Mh4HuvSQWPozJfYAFtQoNnOsxbCek4Gz85DzsOf3g77idHxSvKd9LjMfoATNE8Stg0mfpgV30eSLIASRxQ9A8jEQv6IZbSCbNkksp2JcLnkoyzXtJ0+p/ds2R0T1Q+UEPy8P6w678nsRidp3swD/UKKRBunLYaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p3M3evzh7nd0UM5kn7EQQBVzoLU/BADl28kKfwr+ruA=; b=4/sBd2RR+p2sPRaJn/973Lbq94kdvL2LvepLtXUV5e9iERYbOR8BNGglJBU4uEFhv8Cosycvc26iIYVMYdV6E88MNhURr0JHDDSf1SD3GChi3C+sPMKbUuUy9O+LbmcvGaYgDAt92Mml0xlKn1CAfpr2oDxYl7R9mHIvrlRHMTU= Received: from VI1PR0801MB2127.eurprd08.prod.outlook.com (10.168.62.22) by VI1PR0801MB2000.eurprd08.prod.outlook.com (10.173.76.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2094.15; Wed, 24 Jul 2019 15:16:12 +0000 Received: from VI1PR0801MB2127.eurprd08.prod.outlook.com ([fe80::fd9f:fb0f:dbf2:2304]) by VI1PR0801MB2127.eurprd08.prod.outlook.com ([fe80::fd9f:fb0f:dbf2:2304%6]) with mapi id 15.20.2094.013; Wed, 24 Jul 2019 15:16:11 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd , Richard Earnshaw , "Kyrylo Tkachov" Subject: [PATCH][ARM] Fix low reg issue in Thumb-2 movsi patterns Date: Wed, 24 Jul 2019 15:16:11 +0000 Message-ID: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:VI1PR0801MB2000; x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:3276;OLM:3276; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM; SFS:(10009020)(4636009)(396003)(39860400002)(346002)(376002)(366004)(136003)(54534003)(189003)(199004)(2906002)(7696005)(14454004)(8676002)(25786009)(6916009)(99286004)(316002)(102836004)(305945005)(74316002)(186003)(486006)(26005)(54906003)(6116002)(3846002)(7736002)(6506007)(81166006)(81156014)(14444005)(4326008)(66066001)(68736007)(66446008)(66556008)(256004)(33656002)(66946007)(64756008)(53936002)(66476007)(86362001)(76116006)(5660300002)(52536014)(478600001)(71190400001)(476003)(9686003)(71200400001)(6436002)(8936002)(55016002); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0801MB2000; H:VI1PR0801MB2127.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info-Original: B4R146TV7d8HDq7Hqblx+j4cES3KgEPnQ4Vy9Up23u9pC9iH8YBzMHY/RAQ/i1ZgH+V5pQWYtZ8bjz/08StFYs5vefuhqhkBLejm/wWV3lbzI7Vpdp6KJns+t9V35cqwm9edFwJ9xiL9Vq1p1lEVmAm44Qgyvwn2gGiiTOe1WGcWherfhpeWJoG7kngdiMqmdPKwq3xsBsFVExIW/r+Xk71O7Umbybt7LdVc/1R8JyUPsxyQ6IZf0FYcx9NS0cb1+mBGFcpux9rR6mbfgicfRBpcZ2AJkm2MIeN3rozGMp8b21tI9KgSIirlNX1H8Wncn+1Timw5pyA7n+MDk6IuJOdy1+atxPTXXgFgxOli7xfXHpw5GpBQ1ilANBQba/3w0ClrwurK2amqFYI1cr5t1AJ6Az+ztsn8bMhGL1qSHNc= MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT006.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: b9ab7d2f-62e2-499c-34e2-08d71049dcd3 The Thumb-2 movsi patterns try to prefer low registers for loads and stores. However this is done incorrectly by using 2 separate variants with 'l' and 'h' register classes. The register allocator will only use low registers, and as a result we end up with significantly more spills and moves to high registers. Fix this by merging the alternatives and use 'l*r' to indicate preference for low registers. This saves ~400 instructions from the pr77308 testcase. Bootstrap & regress OK on arm-none-linux-gnueabihf --with-cpu=cortex-a57 ChangeLog: 2019-07-24 Wilco Dijkstra * config/arm/thumb2.md (thumb2_movsi_insn): Fix load/store low reg. * config/arm/vfp.md (thumb2_movsi_vfp): Likewise. diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 78a6ea0b10dab97ed6651ce62e99cfd7a81722ab..c7000d0772a7e5887b6d05be188e8eb38c97217d 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -247,8 +247,8 @@ (define_insn "*thumb2_pop_single" ;; regs. The high register alternatives are not taken into account when ;; choosing register preferences in order to reflect their expense. (define_insn "*thumb2_movsi_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m") - (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l*rk,m") + (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,l*rk"))] "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" @@ -262,22 +262,20 @@ (define_insn "*thumb2_movsi_insn" case 3: return \"mvn%?\\t%0, #%B1\"; case 4: return \"movw%?\\t%0, %1\"; case 5: - case 6: /* Cannot load it directly, split to load it via MOV / MOVT. */ if (!MEM_P (operands[1]) && arm_disable_literal_pool) return \"#\"; return \"ldr%?\\t%0, %1\"; - case 7: - case 8: return \"str%?\\t%1, %0\"; + case 6: return \"str%?\\t%1, %0\"; default: gcc_unreachable (); } } - [(set_attr "type" "mov_reg,mov_imm,mov_imm,mvn_imm,mov_imm,load_4,load_4,store_4,store_4") - (set_attr "length" "2,4,2,4,4,4,4,4,4") + [(set_attr "type" "mov_reg,mov_imm,mov_imm,mvn_imm,mov_imm,load_4,store_4") + (set_attr "length" "2,4,2,4,4,4,4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no") - (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*") - (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")] + (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no") + (set_attr "pool_range" "*,*,*,*,*,4094,*") + (set_attr "neg_pool_range" "*,*,*,*,*,0,*")] ) (define_insn "tls_load_dot_plus_four" diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index e0aaa7b00bb41c046da4531a293e123c94e8b9a4..b59dd6b71d228e042feda3a3a06d81dd01d200da 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -258,8 +258,8 @@ (define_insn "*arm_movsi_vfp" ;; is chosen with length 2 when the instruction is predicated for ;; arm_restrict_it. (define_insn "*thumb2_movsi_vfp" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv") - (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*UvTu,*t"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l*rk,m,*t, r,*t,*t, *Uv") + (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,l*rk, r,*t,*t,*UvTu,*t"))] "TARGET_THUMB2 && TARGET_HARD_FLOAT && ( s_register_operand (operands[0], SImode) || s_register_operand (operands[1], SImode))" @@ -275,32 +275,30 @@ (define_insn "*thumb2_movsi_vfp" case 4: return \"movw%?\\t%0, %1\"; case 5: - case 6: /* Cannot load it directly, split to load it via MOV / MOVT. */ if (!MEM_P (operands[1]) && arm_disable_literal_pool) return \"#\"; return \"ldr%?\\t%0, %1\"; - case 7: - case 8: + case 6: return \"str%?\\t%1, %0\"; - case 9: + case 7: return \"vmov%?\\t%0, %1\\t%@ int\"; - case 10: + case 8: return \"vmov%?\\t%0, %1\\t%@ int\"; - case 11: + case 9: return \"vmov%?.f32\\t%0, %1\\t%@ int\"; - case 12: case 13: + case 10: case 11: return output_move_vfp (operands); default: gcc_unreachable (); } " [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load_4,load_4,store_4,store_4,f_mcr,f_mrc,fmov,f_loads,f_stores") - (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4") - (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*") - (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] + (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no") + (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load_4,store_4,f_mcr,f_mrc,fmov,f_loads,f_stores") + (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4") + (set_attr "pool_range" "*,*,*,*,*,4094,*,*,*,*,1018,*") + (set_attr "neg_pool_range" "*,*,*,*,*, 0,*,*,*,*,1008,*")] )