From patchwork Fri Aug 22 21:14:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Myers X-Patchwork-Id: 382357 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B3D3E1400EA for ; Sat, 23 Aug 2014 07:14:42 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=l3xfY1KrTc0YaOJ+R/RA5L2HhdrCt6fVus5cV96CkQInYoSMyf 1qWGHCS6JPrv9adKORlKoiJl/9WOdo2D6YD1Hni8kulcEVe2buCvxUQH7kNzUR1M KcppBtN/MPF2+1SpsAUZwqr5fhkEjcafEpFKJgJlZ55Lgsud5WfbV6HCs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=Ez88rG1jGKb9QF2adx4nXoDSiI4=; b=kC8qNklP0DLh9zyivx3G Ifh/cxthdVTH+FuNfFGJCdfQNlk7AOJWnUYYAlX2E7pfw8WQuFaNmqmw/xR++v/Y j18lBVDfFTAojJVaXa7Iyk00KDgMzIsxVReZXU44z3jS7qZdu8MJbqQax/b8tvbp 7wDCFvQ+Hq/EzxxX8tt/2Lw= Received: (qmail 25624 invoked by alias); 22 Aug 2014 21:14:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25607 invoked by uid 89); 22 Aug 2014 21:14:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 22 Aug 2014 21:14:31 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1XKwAF-0004v7-Me from joseph_myers@mentor.com ; Fri, 22 Aug 2014 14:14:27 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 22 Aug 2014 14:14:27 -0700 Received: from digraph.polyomino.org.uk (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.2.247.3; Fri, 22 Aug 2014 22:14:26 +0100 Received: from jsm28 (helo=localhost) by digraph.polyomino.org.uk with local-esmtp (Exim 4.76) (envelope-from ) id 1XKwAC-00067e-It; Fri, 22 Aug 2014 21:14:24 +0000 Date: Fri, 22 Aug 2014 21:14:24 +0000 From: "Joseph S. Myers" To: CC: Subject: Fix ARM ICE for register var asm ("pc") (PR target/60606) Message-ID: MIME-Version: 1.0 PR 60606 reports an ICE on ARM when declaring a register variable in register pc. Discussion in that bug suggests this usage should be considered invalid and give an error. It turns out similar ICEs also occur (after errors) for other cases of invalid register variables. This patch fixes at least the original bug and others I observed in the course of fixing it (there may well be other cases of registers, on ARM and elsewhere, that still create such ICEs). To make pc invalid for register variables, arm_regno_class is changed to return NO_REGS for PC_REGNUM (which is consistent with REG_CLASS_CONTENTS). Testing the scope of the bug showed similar issues for cc in Thumb mode; that is made invalid by making arm_hard_regno_mode_ok disallow it for non-MODE_CC modes (i.e. modes that might apply to a variable). To avoid ICEs after errors, make_decl_rtl is make to clear DECL_ASSEMBLER_NAME and DECL_HARD_REGISTER when a hard register specification turns out to be invalid. cfgexpand.c:expand_one_var is then made to call expand_one_error_var in this case, consistent with other cases of erroneous variables. Tested with no regressions for cross to arm-none-eabi (it also fixes failures of gcc.dg/noncompile/920507-1.c, which is PR 61330). OK to commit? 2014-08-22 Joseph Myers PR target/60606 PR target/61330 * varasm.c (make_decl_rtl): Clear DECL_ASSEMBLER_NAME and DECL_HARD_REGISTER and return for invalid register specifications. * cfgexpand.c (expand_one_var): If expand_one_hard_reg_var clears DECL_HARD_REGISTER, call expand_one_error_var. * config/arm/arm.c (arm_hard_regno_mode_ok): Do not allow CC_REGNUM with non-MODE_CC modes. (arm_regno_class): Return NO_REGS for PC_REGNUM. 2014-08-22 Joseph Myers PR target/60606 PR target/61330 * gcc.dg/torture/pr60606-1.c, gcc.target/arm/pr60606-2.c, gcc.target/arm/pr60606-3.c, gcc.target/arm/pr60606-4.c: New tests. Index: gcc/cfgexpand.c =================================================================== --- gcc/cfgexpand.c (revision 214225) +++ gcc/cfgexpand.c (working copy) @@ -1307,7 +1307,12 @@ expand_one_var (tree var, bool toplevel, bool real else if (TREE_CODE (var) == VAR_DECL && DECL_HARD_REGISTER (var)) { if (really_expand) - expand_one_hard_reg_var (var); + { + expand_one_hard_reg_var (var); + if (!DECL_HARD_REGISTER (var)) + /* Invalid register specification. */ + expand_one_error_var (var); + } } else if (use_register_for_decl (var)) { Index: gcc/testsuite/gcc.dg/torture/pr60606-1.c =================================================================== --- gcc/testsuite/gcc.dg/torture/pr60606-1.c (revision 0) +++ gcc/testsuite/gcc.dg/torture/pr60606-1.c (revision 0) @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-ffat-lto-objects" } */ + +int +f (void) +{ + register unsigned int r asm ("no-such-register"); /* { dg-error "invalid register name" } */ + return r; +} Index: gcc/testsuite/gcc.target/arm/pr60606-2.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr60606-2.c (revision 0) +++ gcc/testsuite/gcc.target/arm/pr60606-2.c (revision 0) @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +int +f (void) +{ + register unsigned pc asm ("pc"); /* { dg-error "not general enough" } */ + + return pc > 0x12345678; +} Index: gcc/testsuite/gcc.target/arm/pr60606-3.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr60606-3.c (revision 0) +++ gcc/testsuite/gcc.target/arm/pr60606-3.c (revision 0) @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +int +f (void) +{ + register unsigned int r asm ("cc"); /* { dg-error "not general enough|suitable for data type" } */ + return r; +} Index: gcc/testsuite/gcc.target/arm/pr60606-4.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr60606-4.c (revision 0) +++ gcc/testsuite/gcc.target/arm/pr60606-4.c (revision 0) @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +int +f (void) +{ + register unsigned int r[50] asm ("r1"); /* { dg-error "suitable for a register" } */ + return r[1]; +} Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 214225) +++ gcc/config/arm/arm.c (working copy) @@ -22969,6 +22969,9 @@ arm_hard_regno_mode_ok (unsigned int regno, enum m || (TARGET_HARD_FLOAT && TARGET_VFP && regno == VFPCC_REGNUM)); + if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC) + return false; + if (TARGET_THUMB1) /* For the Thumb we only allow values bigger than SImode in registers 0 - 6, so that there is always a second low @@ -23065,6 +23068,9 @@ arm_modes_tieable_p (enum machine_mode mode1, enum enum reg_class arm_regno_class (int regno) { + if (regno == PC_REGNUM) + return NO_REGS; + if (TARGET_THUMB1) { if (regno == STACK_POINTER_REGNUM) Index: gcc/varasm.c =================================================================== --- gcc/varasm.c (revision 214225) +++ gcc/varasm.c (working copy) @@ -1372,6 +1372,11 @@ make_decl_rtl (tree decl) /* As a register variable, it has no section. */ return; } + /* Avoid internal errors from invalid register + specifications. */ + SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE); + DECL_HARD_REGISTER (decl) = 0; + return; } /* Now handle ordinary static variables and functions (in memory). Also handle vars declared register invalidly. */