From patchwork Thu Sep 14 15:24:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 1834296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=w19YFHfQ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rmh2z1gsRz1yhZ for ; Fri, 15 Sep 2023 01:25:15 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 16B533857C4F for ; Thu, 14 Sep 2023 15:25:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 16B533857C4F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694705113; bh=h1pqwPCK3vny67vv2SnwCEjjU+zz+45OAALbO/Ui300=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=w19YFHfQXUw0jB090paZVdcwo3K2zD6oYHSLmA6Jr/g8i+rQ/IsZFQgbNAjdCYHxr KESSmNp7v+mgso1svtfAHhsbM54M7kukneBnbbawAADNslStaUNwDbcVUy8D/b9Q/q alJFt4g6pNLaEyIlBB2VjEMy4Q4LtCBZjLL/+WGw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2089.outbound.protection.outlook.com [40.107.7.89]) by sourceware.org (Postfix) with ESMTPS id 7D68B3858CDA for ; Thu, 14 Sep 2023 15:24:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7D68B3858CDA Received: from AS9PR06CA0306.eurprd06.prod.outlook.com (2603:10a6:20b:45b::15) by AM7PR08MB5301.eurprd08.prod.outlook.com (2603:10a6:20b:dd::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.19; Thu, 14 Sep 2023 15:24:49 +0000 Received: from AM7EUR03FT017.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:45b:cafe::4b) by AS9PR06CA0306.outlook.office365.com (2603:10a6:20b:45b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.19 via Frontend Transport; Thu, 14 Sep 2023 15:24:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT017.mail.protection.outlook.com (100.127.140.184) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.19 via Frontend Transport; Thu, 14 Sep 2023 15:24:49 +0000 Received: ("Tessian outbound d084e965c4eb:v175"); Thu, 14 Sep 2023 15:24:49 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 63e04225ee1c5865 X-CR-MTA-TID: 64aa7808 Received: from af99c8c10323.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 758DBDAF-D0A4-44FF-AEF9-03CE5A8D91B2.1; Thu, 14 Sep 2023 15:24:43 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id af99c8c10323.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 14 Sep 2023 15:24:43 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bQI1we+jvSzp/4FwBvlOfHwSyxdiRcRIxmFNyHe2og7lfwaO+4HkM80mEED1PDQfBJCSYEbf22+eIZsuvbmQ5CZroei1d+As4IecZYVt03ygtHD0g4mDMyKknlZsbPX2OWp8lY1Vl0cAD9kV5NB506ViwfWNKXE+ssFBGFi/p30PB92eWGq2FNa+/P/b9CHze0U+Ko3RUYgbuKCMJYqx0bvfGUtj4fAgcqIqblNWQ4CJ4GDvU2I7Ko+/QyU7fmGxnx+z5JHBCc9jmxMKP3YDzWTUXvVKaLfHHbS/x6k31FKG1DBohq0Omgk5d4a9VSvXZAqI6085kFjUcu/B0j74og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=h1pqwPCK3vny67vv2SnwCEjjU+zz+45OAALbO/Ui300=; b=U2C0ZaByEwTCpMB6w8Lu4j9hZN3wb60QW6SMQFe+m9piheVKRDS/WNjItuFeLwNlqm9Sica+yCx34W3zPl9aYN3aWR2T3e4FtOXgj1B/o4iLhzjPa/3zIUk94E2GjkEzqmgHCy/x9BBphnkyEQHXEbh7mIcD+++nM5zMnlKWqLlekva5iLhUffMve1rfCGVax6DH/Ttdih7seKQF/HQh6Wjarlo1lXEJTIl4fgPQHNF1XnTTnpHv/kITlxHIKyzhK89Q2AfwKHyaFE8Obo6J4uar9hG436xDModPVRNGc92pfTvt3kswxTt33lEMdPJ5bRBobri/LOBFAK0iDDf9Jg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Received: from PAWPR08MB8982.eurprd08.prod.outlook.com (2603:10a6:102:33f::20) by AM9PR08MB6740.eurprd08.prod.outlook.com (2603:10a6:20b:305::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.20; Thu, 14 Sep 2023 15:24:41 +0000 Received: from PAWPR08MB8982.eurprd08.prod.outlook.com ([fe80::ff3d:6e95:9971:a7e]) by PAWPR08MB8982.eurprd08.prod.outlook.com ([fe80::ff3d:6e95:9971:a7e%5]) with mapi id 15.20.6745.034; Thu, 14 Sep 2023 15:24:40 +0000 To: GCC Patches CC: Richard Sandiford , Kyrylo Tkachov Subject: [PATCH] AArch64: Improve immediate expansion [PR105928] Thread-Topic: [PATCH] AArch64: Improve immediate expansion [PR105928] Thread-Index: AQHZ5x9Gctspx2LYh0+W2piSJ660Xg== Date: Thu, 14 Sep 2023 15:24:38 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAWPR08MB8982:EE_|AM9PR08MB6740:EE_|AM7EUR03FT017:EE_|AM7PR08MB5301:EE_ X-MS-Office365-Filtering-Correlation-Id: d54beaac-b105-4369-ef1a-08dbb536bc64 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: icaKzryJ0vLWQoZmq82Hbw9a/HyC3jZhH9PAHvn3zf8EgadgMCuGQ4uNWTP8POGAy6gtpWSqOUVBJf8B0xUSwgGSPT90hRbUNI+83F19uWuT8dsbkq5hYGmj8zXrO+LkHmtVMSraXMrtX0tkEQXSlEE4E4g6VmtoMG3SzTcYs1srPrV32Hir/HJ7k7yEh6zz8Uvt5SGlUrsPYg+OUjzTHb2wE9AVpsHykjs/qodoqsPmM/dActOCxsSWv5vkqoT7vus0lc+Kj9dgr5AcsjKxSVqk+mIDTA7hqbjNLBGAKjN/HqJEpAeEwHY6SuMJ5HbhqPxmggjim/mdFxE4Jlls7HpgU5TPN+VNaMlkWcSm48hM+0ffOjz8cw54K4SBML2G3n+O2ARukfLhc+YACI1DW/AzndD57/+FnzdZwL0YTNXK5JxI2mJtMm2cezd6BSE9/cWeWt3rFGvTD6E8HXgjyf/bc8RS4Lu3YJ8eZNe0EVcqSVRRmT5XSbJG2a7foWjMA/dcONqhAFSoBT/f9Z/FkJjyiIgybj1bHyBXWn5wyFjYjP3bPYpqht0EdTJhGwqWXLqyIbKvvubLkIDvsVQShatnpxb0GN75D+CGAF1FN5QnWaJu6+/Aw0UUQmCg6in9N06K2hYbVJQIZIR+oRJUNJNWYP3KJRrHPUtKumeDvFQ= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAWPR08MB8982.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(366004)(376002)(136003)(346002)(39860400002)(186009)(1800799009)(451199024)(14773004)(84970400001)(41300700001)(2906002)(38100700002)(8676002)(33656002)(86362001)(5660300002)(38070700005)(55016003)(122000001)(52536014)(8936002)(4326008)(7696005)(9686003)(26005)(6506007)(71200400001)(76116006)(54906003)(66476007)(64756008)(66556008)(66946007)(91956017)(316002)(478600001)(66446008)(6916009); DIR:OUT; SFP:1101; MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6740 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 3093d05e-05ba-4c6e-c087-08dbb536b5ad X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6VK8BIKzDIY+gKsXCuril7fNwdaAv0EiUAUFaVSHMw0Cio8VKYke9urf3cpL7j52DzNGmYF87Oap1GK03jAW5TYcPTsSwQ0TuOpcRzJOu0GdVRELWaWdAF3stt4BWG4Qbpc1wIMqziLsgp4d+8sOgJTT1g56VImFHYLGOmtgchtqXxBy2JLIORqv+FXv2xTX70Pg5MRUrXD2Y7pQRW8u1YWUzquYU5LAxpwTwLFpzBXsDPqsvYHMcwm6Heqe7x3HwpwPYaBO3lM1G+iQy2zZCGIYJEhRbu6ln6Z+tH2YWiyp7A+smPDvkTLMdqywoW0U2jB7whh4BKokWkHfasJ1VbX5v9Y3ekoY8ADM7Ulhyqww1eyI2xFOsMRdjy+I9l1RkJ5uzE8sQFmiod2E2ZRVxyXWtfcKIQBdzoz/RDfy90dv6m/IIE98pZwgiddxSJfj1kvo5qa2Xps3otkAiNF7e2hMW+GrfZMh1hzX+u//4Lj+W3IFLbdX15kZyTpPVNXUWAzjEg9xhOnZjlvBEzvZdUEpdJbzGvsOi04aY5dbBDSJgJi02BXlY9320OWCnzZop3twbBQOEpuvDJDMO4z5fohuS6c2NZ71BYbvriK/+UKpCI4F4tCW/wVmqc8Q6NMz53C8qUjIWs0PnfOjqvRBMJaFzY2/ppRfHJQK7kPvpIdY1F4CHyvFW4VYC6zrpjrnuH+aQfcAnUPH2etzrD2+ApalCqSnDmNup6tdE+Pi0MoQIXfNfx9du8exQXvGIyfd3YdNPRShlZiWVt/EJzEl9Wqt+BKntppFgYBy67+v9u0= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(396003)(376002)(136003)(346002)(82310400011)(1800799009)(451199024)(186009)(36840700001)(40470700004)(46966006)(47076005)(36860700001)(84970400001)(40460700003)(478600001)(55016003)(40480700001)(5660300002)(54906003)(52536014)(70586007)(70206006)(336012)(8936002)(14773004)(4326008)(8676002)(41300700001)(2906002)(81166007)(86362001)(356005)(6916009)(316002)(82740400003)(9686003)(33656002)(26005)(6506007)(7696005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2023 15:24:49.5868 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d54beaac-b105-4369-ef1a-08dbb536bc64 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR08MB5301 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Wilco Dijkstra via Gcc-patches From: Wilco Dijkstra Reply-To: Wilco Dijkstra Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Support immediate expansion of immediates which can be created from 2 MOVKs and a shifted ORR or BIC instruction. Change aarch64_split_dimode_const_store to apply if we save one instruction. This reduces the number of 4-instruction immediates in SPECINT/FP by 5%. Passes regress, OK for commit? gcc/ChangeLog: PR target/105928 * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate) Add support for immediates using shifted ORR/BIC. (aarch64_split_dimode_const_store): Apply if we save one instruction. * config/aarch64/aarch64.md (_3): Make pattern global. gcc/testsuite: PR target/105928 * gcc.target/aarch64/pr105928.c: Add new test. * gcc.target/aarch64/vect-cse-codegen.c: Fix test. diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index c44c0b979d0cc3755c61dcf566cfddedccebf1ea..832f8197ac8d1a04986791e6f3e51861e41944b2 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -5639,7 +5639,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate, machine_mode mode) { int i; - unsigned HOST_WIDE_INT val, val2, mask; + unsigned HOST_WIDE_INT val, val2, val3, mask; int one_match, zero_match; int num_insns; @@ -5721,6 +5721,35 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate, } return 3; } + + /* Try shifting and inserting the bottom 32-bits into the top bits. */ + val2 = val & 0xffffffff; + val3 = 0xffffffff; + val3 = val2 | (val3 << 32); + for (i = 17; i < 48; i++) + if ((val2 | (val2 << i)) == val) + { + if (generate) + { + emit_insn (gen_rtx_SET (dest, GEN_INT (val2 & 0xffff))); + emit_insn (gen_insv_immdi (dest, GEN_INT (16), + GEN_INT (val2 >> 16))); + emit_insn (gen_ior_ashldi3 (dest, dest, GEN_INT (i), dest)); + } + return 3; + } + else if ((val3 & ~(val3 << i)) == val) + { + if (generate) + { + emit_insn (gen_rtx_SET (dest, GEN_INT (val3 | 0xffff0000))); + emit_insn (gen_insv_immdi (dest, GEN_INT (16), + GEN_INT (val2 >> 16))); + emit_insn (gen_and_one_cmpl_ashldi3 (dest, dest, GEN_INT (i), + dest)); + } + return 3; + } } /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which @@ -25506,8 +25535,6 @@ aarch64_split_dimode_const_store (rtx dst, rtx src) rtx lo = gen_lowpart (SImode, src); rtx hi = gen_highpart_mode (SImode, DImode, src); - bool size_p = optimize_function_for_size_p (cfun); - if (!rtx_equal_p (lo, hi)) return false; @@ -25526,14 +25553,8 @@ aarch64_split_dimode_const_store (rtx dst, rtx src) MOV w1, 49370 MOVK w1, 0x140, lsl 16 STP w1, w1, [x0] - So we want to perform this only when we save two instructions - or more. When optimizing for size, however, accept any code size - savings we can. */ - if (size_p && orig_cost <= lo_cost) - return false; - - if (!size_p - && (orig_cost <= lo_cost + 1)) + So we want to perform this when we save at least one instruction. */ + if (orig_cost <= lo_cost) return false; rtx mem_lo = adjust_address (dst, SImode, 0); diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 97f70d39cc0ddeb330e044bae0544d85a695567d..932d4d47a5db1a74e0d0565b565afbd769090853 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4618,7 +4618,7 @@ (define_insn "*and_si3_compare0_uxtw" [(set_attr "type" "logics_shift_imm")] ) -(define_insn "*_3" +(define_insn "_3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI (match_operand:GPI 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/aarch64/pr105928.c b/gcc/testsuite/gcc.target/aarch64/pr105928.c new file mode 100644 index 0000000000000000000000000000000000000000..ab52247df66020d0b8fe70bc81f572e8b64c2bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr105928.c @@ -0,0 +1,43 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 --save-temps" } */ + +long f1 (void) +{ + return 0x80402010080400; +} + +long f2 (void) +{ + return 0x1234567812345678; +} + +long f3 (void) +{ + return 0x4567800012345678; +} + +long f4 (void) +{ + return 0x3ecccccd3ecccccd; +} + +long f5 (void) +{ + return 0x38e38e38e38e38e; +} + +long f6 (void) +{ + return 0x1745d1745d1745d; +} + +void f7 (long *p) +{ + *p = 0x1234567812345678; +} + +/* { dg-final { scan-assembler-times {\tmovk\t} 7 } } */ +/* { dg-final { scan-assembler-times {\tmov\t} 7 } } */ +/* { dg-final { scan-assembler-times {\tbic\t} 2 } } */ +/* { dg-final { scan-assembler-times {\torr\t} 4 } } */ +/* { dg-final { scan-assembler-times {\tstp\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-cse-codegen.c b/gcc/testsuite/gcc.target/aarch64/vect-cse-codegen.c index d025e989a1e67f00f4f4ce94897a961d38abfab7..2b8e64313bb47f995f071c728b1d84473807bc64 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-cse-codegen.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-cse-codegen.c @@ -72,8 +72,7 @@ test3 (uint32_t a, uint32x4_t b, uint32x4_t* rt) ** ushr v[0-9]+.16b, v[0-9]+.16b, 7 ** mov x[0-9]+, 16512 ** movk x[0-9]+, 0x1020, lsl 16 -** movk x[0-9]+, 0x408, lsl 32 -** movk x[0-9]+, 0x102, lsl 48 +** orr x[0-9]+, x[0-9]+, x[0-9]+, lsl 28 ** fmov d[0-9]+, x[0-9]+ ** pmull v[0-9]+.1q, v[0-9]+.1d, v[0-9]+.1d ** dup v[0-9]+.2d, v[0-9]+.d\[0\]