diff mbox series

AArch64: Add -mcpu=cobalt-100

Message ID PAWPR08MB89826A88BC9275089F005A3D83732@PAWPR08MB8982.eurprd08.prod.outlook.com
State New
Headers show
Series AArch64: Add -mcpu=cobalt-100 | expand

Commit Message

Wilco Dijkstra Jan. 16, 2024, 5:23 p.m. UTC 
Add support for -mcpu=cobalt-100 (Neoverse N2 with a different implementer ID).

Passes regress, OK for commit?

gcc/ChangeLog:
        * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
        * config/aarch64/aarch64-tune.md: Regenerated.
        * doc/invoke.texi (-mcpu): Add cobalt-100 core.

---

Comments

Kyrylo Tkachov Jan. 16, 2024, 5:34 p.m. UTC | #1 
> -----Original Message-----
> From: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
> Sent: Tuesday, January 16, 2024 5:23 PM
> To: GCC Patches <gcc-patches@gcc.gnu.org>
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Subject: [PATCH] AArch64: Add -mcpu=cobalt-100
> 
> 
> Add support for -mcpu=cobalt-100 (Neoverse N2 with a different implementer
> ID).
> 
> Passes regress, OK for commit?

Ok.
Thanks,
Kyrill

> 
> gcc/ChangeLog:
>         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100'
> CPU.
>         * config/aarch64/aarch64-tune.md: Regenerated.
>         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
> 
> ---
> 
> diff --git a/gcc/config/aarch64/aarch64-cores.def
> b/gcc/config/aarch64/aarch64-cores.def
> index
> 054862f37bc8738e7193348d01f485a46a9a36e3..7ebefcf543b6f84b3df22ab8367
> 28111b56fa76f 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -186,6 +186,7 @@ AARCH64_CORE("cortex-x3",  cortexx3, cortexa57, V9A,
> (SVE2_BITPERM, MEMTAG, I8M
>  AARCH64_CORE("cortex-x4",  cortexx4, cortexa57, V9_2A,  (SVE2_BITPERM,
> MEMTAG, PROFILE), neoversen2, 0x41, 0xd81, -1)
> 
>  AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16,
> SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
> +AARCH64_CORE("cobalt-100",   cobalt100, cortexa57, V9A, (I8MM, BF16,
> SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x6d, 0xd49, -1)
> 
>  AARCH64_CORE("neoverse-v2", neoversev2, cortexa57, V9A, (I8MM, BF16,
> SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1)
>  AARCH64_CORE("demeter", demeter, cortexa57, V9A, (I8MM, BF16,
> SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1)
> diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-
> tune.md
> index
> 98e6882d4324d81268e28810b305b87c63bba22d..abd3c9e0822eeb1652f4856cd
> e591ac175ac0a4a 100644
> --- a/gcc/config/aarch64/aarch64-tune.md
> +++ b/gcc/config/aarch64/aarch64-tune.md
> @@ -1,5 +1,5 @@
>  ;; -*- buffer-read-only: t -*-
>  ;; Generated automatically by gentune.sh from aarch64-cores.def
>  (define_attr "tune"
> -
> 	"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,
> thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thun
> derxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,ph
> ecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> a76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortex
> x1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,
> octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunde
> rx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72c
> ortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76c
> ortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cor
> texx2,cortexx3,cortexx4,neoversen2,neoversev2,demeter,generic,generic_armv8
> _a,generic_armv9_a"
> +
> 	"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,
> thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thun
> derxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,ph
> ecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> a76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortex
> x1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,
> octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunde
> rx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72c
> ortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76c
> ortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cor
> texx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,gene
> ric_armv8_a,generic_armv9_a"
>  	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index
> 216e2f594d1cbc139c7e0125d9579c6924d23443..a25362b8c157f67d68b19f94cc
> 2d64bd09505bdc 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -21163,7 +21163,7 @@ performance of the code.  Permissible values for this
> option are:
>  @samp{cortex-r82}, @samp{cortex-x1}, @samp{cortex-x1c}, @samp{cortex-x2},
>  @samp{cortex-x3}, @samp{cortex-x4}, @samp{cortex-a510}, @samp{cortex-
> a520},
>  @samp{cortex-a710}, @samp{cortex-a715}, @samp{cortex-a720},
> @samp{ampere1},
> -@samp{ampere1a}, @samp{ampere1b}, and @samp{native}.
> +@samp{ampere1a}, @samp{ampere1b}, @samp{cobalt-100} and
> @samp{native}.
> 
>  The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
>  @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53},
>
Wilco Dijkstra Jan. 25, 2024, 5 p.m. UTC | #2 
Hi,

>> Add support for -mcpu=cobalt-100 (Neoverse N2 with a different implementer
>> ID).
>> 
>> Passes regress, OK for commit?
>
> Ok.

Also OK to backport to GCC 13, 12 and 11?

Cheers,
Wilco
Kyrylo Tkachov Jan. 25, 2024, 5:17 p.m. UTC | #3 
> -----Original Message-----
> From: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
> Sent: Thursday, January 25, 2024 5:00 PM
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; GCC Patches <gcc-
> patches@gcc.gnu.org>
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Subject: Re: [PATCH] AArch64: Add -mcpu=cobalt-100
> 
> Hi,
> 
> >> Add support for -mcpu=cobalt-100 (Neoverse N2 with a different implementer
> >> ID).
> >>
> >> Passes regress, OK for commit?
> >
> > Ok.
> 
> Also OK to backport to GCC 13, 12 and 11?

On the 11 branch at least there is no support for the armv9-a flags, so the aarch64-cores.def entry would need to use what the branch-local neoverse-n2 entry uses (armv8.5-a).
So the trunk patch won't apply as is.
So please ensure the appropriate flags are used in the aarch64-cores.def entry (with the usual testing).
But otherwise it's okay.
Thanks,
Kyrill

> 
> Cheers,
> Wilco
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 054862f37bc8738e7193348d01f485a46a9a36e3..7ebefcf543b6f84b3df22ab836728111b56fa76f 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -186,6 +186,7 @@  AARCH64_CORE("cortex-x3",  cortexx3, cortexa57, V9A,  (SVE2_BITPERM, MEMTAG, I8M
 AARCH64_CORE("cortex-x4",  cortexx4, cortexa57, V9_2A,  (SVE2_BITPERM, MEMTAG, PROFILE), neoversen2, 0x41, 0xd81, -1)
 
 AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
+AARCH64_CORE("cobalt-100",   cobalt100, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x6d, 0xd49, -1)
 
 AARCH64_CORE("neoverse-v2", neoversev2, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1)
 AARCH64_CORE("demeter", demeter, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index 98e6882d4324d81268e28810b305b87c63bba22d..abd3c9e0822eeb1652f4856cde591ac175ac0a4a 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@ 
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-	"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a"
+	"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,cobalt100,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a"
 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 216e2f594d1cbc139c7e0125d9579c6924d23443..a25362b8c157f67d68b19f94cc2d64bd09505bdc 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21163,7 +21163,7 @@  performance of the code.  Permissible values for this option are:
 @samp{cortex-r82}, @samp{cortex-x1}, @samp{cortex-x1c}, @samp{cortex-x2},
 @samp{cortex-x3}, @samp{cortex-x4}, @samp{cortex-a510}, @samp{cortex-a520},
 @samp{cortex-a710}, @samp{cortex-a715}, @samp{cortex-a720}, @samp{ampere1},
-@samp{ampere1a}, @samp{ampere1b}, and @samp{native}.
+@samp{ampere1a}, @samp{ampere1b}, @samp{cobalt-100} and @samp{native}.
 
 The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
 @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53},