diff mbox

Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439

Message ID F007E4D1AE275F468C186A52E051529CE4564F4F@BADAG02.ba.imgtec.org
State New
Headers show

Commit Message

Doug Gilmore Oct. 1, 2016, 1:35 a.m. UTC 
My commit r240439 didn't handle the situation where setting
--param prefetch-latency=0 can cause the prefetch address to
be the same as the original address.  In this case, no
copying of points-to information should be done.

Bootstrapped and regression tested on x86_64-linux, ok for
trunk?

Doug

Comments

Christophe Lyon Oct. 1, 2016, 2:57 p.m. UTC | #1 
Hi Doug,


On 1 October 2016 at 03:35, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
> My commit r240439 didn't handle the situation where setting
> --param prefetch-latency=0 can cause the prefetch address to
> be the same as the original address.  In this case, no
> copying of points-to information should be done.
>
> Bootstrapped and regression tested on x86_64-linux, ok for
> trunk?
>
> Doug

I can confirm that your patch fixes the ICE I was seeing.

However, the new testcase does not pass on low end
architectures:
cc1: warning: -fprefetch-loop-arrays not supported for this target
(try -march switches)

Can you add a guard?

Thanks,

Christophe
Doug Gilmore Oct. 2, 2016, 9:05 p.m. UTC | #2 
Hi Christophe,

> From: Christophe Lyon [christophe.lyon@linaro.org]
> Sent: Saturday, October 01, 2016 7:57 AM
> To: Doug Gilmore
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
> 
> Hi Doug,
>
> ...
> I can confirm that your patch fixes the ICE I was seeing.
> 
> However, the new testcase does not pass on low end
> architectures:
> cc1: warning: -fprefetch-loop-arrays not supported for this target
> (try -march switches)
> 
> Can you add a guard?
> 
> Thanks,
> 
> Christophe
I updated the test to only run on X86, MIPS and AARCH64.  Is that OK?

Thanks,

Doug
Christophe Lyon Oct. 3, 2016, 7:05 a.m. UTC | #3 
On 2 October 2016 at 23:05, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
> Hi Christophe,
>
>> From: Christophe Lyon [christophe.lyon@linaro.org]
>> Sent: Saturday, October 01, 2016 7:57 AM
>> To: Doug Gilmore
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>
>> Hi Doug,
>>
>> ...
>> I can confirm that your patch fixes the ICE I was seeing.
>>
>> However, the new testcase does not pass on low end
>> architectures:
>> cc1: warning: -fprefetch-loop-arrays not supported for this target
>> (try -march switches)
>>
>> Can you add a guard?
>>
>> Thanks,
>>
>> Christophe
> I updated the test to only run on X86, MIPS and AARCH64.  Is that OK?
>

I'm afraid not.

The ICE occurred on some arm targets. By "low end" I meant armv5t for
example, as opposed to armv7t.
Is there a suitable effective target?

Thanks,

Christophe

> Thanks,
>
> Doug
Doug Gilmore Oct. 3, 2016, 4:07 p.m. UTC | #4 
>From: Christophe Lyon [christophe.lyon@linaro.org]
>Sent: Monday, October 03, 2016 12:05 AM
>To: Doug Gilmore
>Cc: gcc-patches@gcc.gnu.org
>Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>
>On 2 October 2016 at 23:05, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>> Hi Christophe,
>>
>>> From: Christophe Lyon [christophe.lyon@linaro.org]
>>> Sent: Saturday, October 01, 2016 7:57 AM
>>> To: Doug Gilmore
>>> Cc: gcc-patches@gcc.gnu.org
>>> Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>>
>>> Hi Doug,
>>>
>>> ...
>>> I can confirm that your patch fixes the ICE I was seeing.
>>>
>>> However, the new testcase does not pass on low end
>>> architectures:
>>> cc1: warning: -fprefetch-loop-arrays not supported for this target
>>> (try -march switches)
>>>
>>> Can you add a guard?
>>>
>>> Thanks,
>>>
>>> Christophe
>> I updated the test to only run on X86, MIPS and AARCH64.  Is that OK?
>>
>
>I'm afraid not.
>
>The ICE occurred on some arm targets. By "low end" I meant armv5t for
>example, as opposed to armv7t.
>Is there a suitable effective target?
I'll need to investigate that.  BTW, gcc.dg/pr53550.c contains:
/* PR tree-optimization/53550 */
/* { dg-do compile } */
/* { dg-options "-O2 -fprefetch-loop-arrays -w" } */

int *
foo (int *x)
{
  int *a = x + 10, *b = x, *c = a;
  while (b != c)
    *--c = *b++;
  return x;
}

Is it also failing on armv5t?  I suppose it would.

Thanks,

Doug
>
>Thanks,
>
>Christophe
>
>> Thanks,
>>
>> Doug
Christophe Lyon Oct. 3, 2016, 6:23 p.m. UTC | #5 
On 3 October 2016 at 18:07, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>>From: Christophe Lyon [christophe.lyon@linaro.org]
>>Sent: Monday, October 03, 2016 12:05 AM
>>To: Doug Gilmore
>>Cc: gcc-patches@gcc.gnu.org
>>Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>
>>On 2 October 2016 at 23:05, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>>> Hi Christophe,
>>>
>>>> From: Christophe Lyon [christophe.lyon@linaro.org]
>>>> Sent: Saturday, October 01, 2016 7:57 AM
>>>> To: Doug Gilmore
>>>> Cc: gcc-patches@gcc.gnu.org
>>>> Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>>>
>>>> Hi Doug,
>>>>
>>>> ...
>>>> I can confirm that your patch fixes the ICE I was seeing.
>>>>
>>>> However, the new testcase does not pass on low end
>>>> architectures:
>>>> cc1: warning: -fprefetch-loop-arrays not supported for this target
>>>> (try -march switches)
>>>>
>>>> Can you add a guard?
>>>>
>>>> Thanks,
>>>>
>>>> Christophe
>>> I updated the test to only run on X86, MIPS and AARCH64.  Is that OK?
>>>
>>
>>I'm afraid not.
>>
>>The ICE occurred on some arm targets. By "low end" I meant armv5t for
>>example, as opposed to armv7t.
>>Is there a suitable effective target?
> I'll need to investigate that.  BTW, gcc.dg/pr53550.c contains:
> /* PR tree-optimization/53550 */
> /* { dg-do compile } */
> /* { dg-options "-O2 -fprefetch-loop-arrays -w" } */
>
> int *
> foo (int *x)
> {
>   int *a = x + 10, *b = x, *c = a;
>   while (b != c)
>     *--c = *b++;
>   return x;
> }
>
> Is it also failing on armv5t?  I suppose it would.
>
It doesn't, but that's probably thanks to -w

Christophe

> Thanks,
>
> Doug
>>
>>Thanks,
>>
>>Christophe
>>
>>> Thanks,
>>>
>>> Doug
Doug Gilmore Oct. 3, 2016, 6:36 p.m. UTC | #6 
>From: Christophe Lyon [christophe.lyon@linaro.org]
>Sent: Monday, October 03, 2016 11:23 AM
>To: Doug Gilmore
>Cc: gcc-patches@gcc.gnu.org
>Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>
>On 3 October 2016 at 18:07, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>>>From: Christophe Lyon [christophe.lyon@linaro.org]
>>>Sent: Monday, October 03, 2016 12:05 AM
>>>To: Doug Gilmore
>>>Cc: gcc-patches@gcc.gnu.org
>>>Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>>
>>>On 2 October 2016 at 23:05, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>>>> Hi Christophe,
>>>>
>>>>> From: Christophe Lyon [christophe.lyon@linaro.org]
>>>>> Sent: Saturday, October 01, 2016 7:57 AM
>>>>> To: Doug Gilmore
>>>>> Cc: gcc-patches@gcc.gnu.org
>>>>> Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>>>>
>>>>> Hi Doug,
>>>>>
>>>>> ...
>>>>> I can confirm that your patch fixes the ICE I was seeing.
>>>>>
>>>>> However, the new testcase does not pass on low end
>>>>> architectures:
>>>>> cc1: warning: -fprefetch-loop-arrays not supported for this target
>>>>> (try -march switches)
>>>>>
>>>>> Can you add a guard?
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Christophe
>>>> I updated the test to only run on X86, MIPS and AARCH64.  Is that OK?
>>>>
>>>
>>>I'm afraid not.
>>>
>>>The ICE occurred on some arm targets. By "low end" I meant armv5t for
>>>example, as opposed to armv7t.
>>>Is there a suitable effective target?
>> I'll need to investigate that.  BTW, gcc.dg/pr53550.c contains:
>> /* PR tree-optimization/53550 */
>> /* { dg-do compile } */
>> /* { dg-options "-O2 -fprefetch-loop-arrays -w" } */
>>
>> int *
>> foo (int *x)
>> {
>>   int *a = x + 10, *b = x, *c = a;
>>   while (b != c)
>>     *--c = *b++;
>>   return x;
>> }
>>
>> Is it also failing on armv5t?  I suppose it would.
>>
>It doesn't, but that's probably thanks to -w
Sounds like we don't need add guards then, it is just a matter
of adding -w to the command line.

Does that work for you?

Thanks,

Doug
>
>Christophe
>
>> Thanks,
>>
>> Doug
>>>
>>>Thanks,
>>>
>>>Christophe
>>>
>>>> Thanks,
>>>>
>>>> Doug
Christophe Lyon Oct. 4, 2016, 6:28 a.m. UTC | #7 
On 3 October 2016 at 20:36, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>>From: Christophe Lyon [christophe.lyon@linaro.org]
>>Sent: Monday, October 03, 2016 11:23 AM
>>To: Doug Gilmore
>>Cc: gcc-patches@gcc.gnu.org
>>Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>
>>On 3 October 2016 at 18:07, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>>>>From: Christophe Lyon [christophe.lyon@linaro.org]
>>>>Sent: Monday, October 03, 2016 12:05 AM
>>>>To: Doug Gilmore
>>>>Cc: gcc-patches@gcc.gnu.org
>>>>Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>>>
>>>>On 2 October 2016 at 23:05, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
>>>>> Hi Christophe,
>>>>>
>>>>>> From: Christophe Lyon [christophe.lyon@linaro.org]
>>>>>> Sent: Saturday, October 01, 2016 7:57 AM
>>>>>> To: Doug Gilmore
>>>>>> Cc: gcc-patches@gcc.gnu.org
>>>>>> Subject: Re: Fix PR tree-optimization/77808, ICE in duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>>>>>
>>>>>> Hi Doug,
>>>>>>
>>>>>> ...
>>>>>> I can confirm that your patch fixes the ICE I was seeing.
>>>>>>
>>>>>> However, the new testcase does not pass on low end
>>>>>> architectures:
>>>>>> cc1: warning: -fprefetch-loop-arrays not supported for this target
>>>>>> (try -march switches)
>>>>>>
>>>>>> Can you add a guard?
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> Christophe
>>>>> I updated the test to only run on X86, MIPS and AARCH64.  Is that OK?
>>>>>
>>>>
>>>>I'm afraid not.
>>>>
>>>>The ICE occurred on some arm targets. By "low end" I meant armv5t for
>>>>example, as opposed to armv7t.
>>>>Is there a suitable effective target?
>>> I'll need to investigate that.  BTW, gcc.dg/pr53550.c contains:
>>> /* PR tree-optimization/53550 */
>>> /* { dg-do compile } */
>>> /* { dg-options "-O2 -fprefetch-loop-arrays -w" } */
>>>
>>> int *
>>> foo (int *x)
>>> {
>>>   int *a = x + 10, *b = x, *c = a;
>>>   while (b != c)
>>>     *--c = *b++;
>>>   return x;
>>> }
>>>
>>> Is it also failing on armv5t?  I suppose it would.
>>>
>>It doesn't, but that's probably thanks to -w
> Sounds like we don't need add guards then, it is just a matter
> of adding -w to the command line.
>
> Does that work for you?
>

Yes, it does, I verified all the configurations I normally validate.
Adding "-w" to the testcase does the trick.

Thanks,

Christophe

> Thanks,
>
> Doug
>>
>>Christophe
>>
>>> Thanks,
>>>
>>> Doug
>>>>
>>>>Thanks,
>>>>
>>>>Christophe
>>>>
>>>>> Thanks,
>>>>>
>>>>> Doug
Richard Biener Oct. 4, 2016, 8:22 a.m. UTC | #8 
On Sat, Oct 1, 2016 at 3:35 AM, Doug Gilmore <Doug.Gilmore@imgtec.com> wrote:
> My commit r240439 didn't handle the situation where setting
> --param prefetch-latency=0 can cause the prefetch address to
> be the same as the original address.  In this case, no
> copying of points-to information should be done.
>
> Bootstrapped and regression tested on x86_64-linux, ok for
> trunk?

Ok.

RIchard.

> Doug
Matthew Fortune Oct. 4, 2016, 3:29 p.m. UTC | #9 
Richard Biener <richard.guenther@gmail.com> writes:
> On Sat, Oct 1, 2016 at 3:35 AM, Doug Gilmore <Doug.Gilmore@imgtec.com>

> wrote:

> > My commit r240439 didn't handle the situation where setting --param

> > prefetch-latency=0 can cause the prefetch address to be the same as

> > the original address.  In this case, no copying of points-to

> > information should be done.

> >

> > Bootstrapped and regression tested on x86_64-linux, ok for trunk?

> 

> Ok.

> 

> RIchard.


Committed as r240749.

(I updated the changelog to say what changed)

gcc/
        PR tree-optimization/77808
        * tree-ssa-loop-prefetch.c (issue_prefetch_ref): Check base_addr
        and addr are different before copying points-to information.

gcc/testsuite
        PR tree-optimization/77808
        * gcc.dg/tree-ssa/pr77808.c: New testcase.


Matthew
diff mbox

Patch

From d7a115e12856f2bcd4cefab38378f5d947c7d96a Mon Sep 17 00:00:00 2001
From: Doug Gilmore <doug.gilmore@imgtec.com>
Date: Fri, 30 Sep 2016 11:28:20 -0700
Subject: [PATCH] Fix PR tree-optimization/77808

gcc/
	PR tree-optimization/77808
	* tree-ssa-loop-prefetch.c (issue_prefetch_ref): Fix problem
	exposed by specifying --param prefetch-latency=0.

gcc/testsuite
	PR tree-optimization/77808
	* gcc.dg/tree-ssa/pr77808.c: New testcase.
---
 gcc/testsuite/gcc.dg/tree-ssa/pr77808.c | 11 +++++++++++
 gcc/tree-ssa-loop-prefetch.c            |  3 ++-
 2 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr77808.c

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr77808.c b/gcc/testsuite/gcc.dg/tree-ssa/pr77808.c
new file mode 100644
index 0000000..85393f4
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr77808.c
@@ -0,0 +1,11 @@ 
+/* PR tree-optimization/77808 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fprefetch-loop-arrays --param prefetch-latency=0" } */
+
+void daxpy(int n, double da, double * __restrict dx, double * __restrict dy)
+{
+  int i;
+
+  for (i = 0;i < n; i++)
+    dy[i] = dy[i] + da*dx[i];
+}
diff --git a/gcc/tree-ssa-loop-prefetch.c b/gcc/tree-ssa-loop-prefetch.c
index 056815d..43ee85a 100644
--- a/gcc/tree-ssa-loop-prefetch.c
+++ b/gcc/tree-ssa-loop-prefetch.c
@@ -1162,7 +1162,8 @@  issue_prefetch_ref (struct mem_ref *ref, unsigned unroll_factor, unsigned ahead)
 					   NULL, true, GSI_SAME_STMT);
       }
 
-      if (TREE_CODE (addr_base) == SSA_NAME
+      if (addr_base != addr
+	  && TREE_CODE (addr_base) == SSA_NAME
 	  && TREE_CODE (addr) == SSA_NAME)
 	{
 	  duplicate_ssa_name_ptr_info (addr, SSA_NAME_PTR_INFO (addr_base));
-- 
1.9.1