@@ -320,6 +320,38 @@
[(set_attr "type" "no_insn")]
)
+
+(define_insn "prefetch"
+ [(prefetch (match_operand:DI 0 "address_operand" "r")
+ (match_operand:QI 1 "const_int_operand" "")
+ (match_operand:QI 2 "const_int_operand" ""))]
+ ""
+ "*
+{
+ const char * pftype[2][10]
+ = { {\"PLDL1STRM\", \"PLDL3KEEP\", \"PLDL2KEEP\", \"PLDL1KEEP\"},
+ {\"PSTL1STRM\", \"PSTL3KEEP\", \"PSTL2KEEP\", \"PSTL1KEEP\"},
+ };
+
+ int locality = INTVAL (operands[2]);
+ char pattern[100];
+
+ gcc_assert (IN_RANGE (locality, 0, 3));
+
+ strcpy (pattern, \"prfm\\t\");
+ strcat (pattern, (const char*)pftype[INTVAL(operands[1])][locality]);
+ strcat (pattern, \", %a0\");
+
+ output_asm_insn (pattern,
+ operands);
+
+ return \"\";
+
+}"
+ [(set_attr "type" "prefetch")]
+)
+
(define_insn "trap"
[(trap_if (const_int 1) (const_int 8))]
""
@@ -118,6 +118,7 @@
; mvn_shift_reg inverting move instruction, shifted operand by a register.
; no_insn an insn which does not represent an instruction in the ; final output, thus having no impact on scheduling.
+; prefetch a prefetch instruction
; rbit reverse bits.
; rev reverse bytes.
; sdiv signed division.
@@ -556,6 +557,7 @@
PING! I am worried if it goes in stage-1. -----Original Message----- From: Gopalasubramanian, Ganesh Sent: Thursday, October 30, 2014 2:24 PM To: gcc-patches@gcc.gnu.org Subject: [PATCH, aarch64] Add prefetch support Hi, Below is the patch that implements prefetching support. This patch has been already discussed on a) https://gcc.gnu.org/ml/gcc-patches/2014-02/msg01644.html b) https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00612.html I have not added a test as there are ample tests in compile and execute suites. "make -k check" passes. Ok for trunk? Changelog: 2014-10-30 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> * config/aarch64/aarch64.md (define_insn "prefetch"): New. * config/arm/types.md (define_attr "type"): Add prefetch. Regards Ganesh call,\ clz,\ no_insn,\ + prefetch,\ csel,\ crc,\