| Message ID | DM2PR12MB0137C7D2468EE7E84186E27385DF0@DM2PR12MB0137.namprd12.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
On Tue, Feb 2, 2016 at 9:28 PM, Stepanyan, Victoria <Victoria.Stepanyan@amd.com> wrote: > Hi Maintainers, > > This patch disables prefetching for -march=znver1 which is turned on by default. > > gcc/ChangeLog: > > 2016-02-02 Victoria Stepanyan <victoria.stepanyan@amd.com> > > * gcc/config/i386/x86-tune.def: Disable default prefetching for -march=znver1 > > Ok for trunk? OK. Thanks, Uros.
Hi Uros, > -----Original Message----- > From: Uros Bizjak [mailto:ubizjak@gmail.com] > Sent: Wednesday, February 03, 2016 2:20 AM > To: Stepanyan, Victoria > Cc: gcc-patches@gcc.gnu.org; gerald@pfeifer.com; rguenther@suse.de; > Kumar, Venkataramanan > Subject: Re: Turnoff prefetching for -march=znver1 > > On Tue, Feb 2, 2016 at 9:28 PM, Stepanyan, Victoria > <Victoria.Stepanyan@amd.com> wrote: > > Hi Maintainers, > > > > This patch disables prefetching for -march=znver1 which is turned on by > default. > > > > gcc/ChangeLog: > > > > 2016-02-02 Victoria Stepanyan <victoria.stepanyan@amd.com> > > > > * gcc/config/i386/x86-tune.def: Disable default prefetching for - > march=znver1 > > > > Ok for trunk? > > OK. Thank you. I up streamed it on behalf of Victoria. https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=233127 > > Thanks, > Uros. Regards, Venkat.
--- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -218,7 +218,7 @@ DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit", at -O3. For the moment, the prefetching seems badly tuned for Intel chips. */ DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial", - m_K6_GEODE | m_AMD_MULTIPLE) + m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER) /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall on 16-bit immediate moves into memory on Core2 and Corei7. */