From patchwork Fri Jul 28 11:37:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Cheng X-Patchwork-Id: 794810 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-459255-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="w66uHYQL"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xJmzp3VYmz9s5L for ; Fri, 28 Jul 2017 21:37:42 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=URw4YMz8K2c2eErNnNs4AtR/4XMhBvrAarAiEwb84qErUuIbM/ qNiFjRKS31/6tkYJ2uoTEpHl83p1Qb4fbmKKfziToPz5tGV1KUUvkO2vjNaJDrdZ dOfzK4MWrBsxRNQuW/hF7FISO+UbrnWDJ2Hlty5fvMBnatxGNCKPwgEMg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=BNA8Fmyq3hGQE5LX9VC3olFjxbc=; b=w66uHYQLRZ5uNo+/XYnY v0sSlx60Qa1/Gt6PR7qknFAGTc1EkwU+e4s5r3u+ODdoJlHNBc6b4buhkBB9+iyO 0xyvR5QBOrhpPO2tPNcdwX7ns9YtVCVXrgzZcLu3Fy63m/cNQZyBMlWdD8HOLjuE AtNuIXpWkzvLTg/Iwn7XgtQ= Received: (qmail 54567 invoked by alias); 28 Jul 2017 11:37:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 53635 invoked by uid 89); 28 Jul 2017 11:37:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=H*c:HHH X-HELO: EUR01-VE1-obe.outbound.protection.outlook.com Received: from mail-ve1eur01on0043.outbound.protection.outlook.com (HELO EUR01-VE1-obe.outbound.protection.outlook.com) (104.47.1.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 28 Jul 2017 11:37:26 +0000 Received: from DB5PR0801MB2742.eurprd08.prod.outlook.com (10.166.176.26) by DB5PR0801MB2741.eurprd08.prod.outlook.com (10.166.176.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1282.10; Fri, 28 Jul 2017 11:37:23 +0000 Received: from DB5PR0801MB2742.eurprd08.prod.outlook.com ([10.166.176.26]) by DB5PR0801MB2742.eurprd08.prod.outlook.com ([10.166.176.26]) with mapi id 15.01.1282.023; Fri, 28 Jul 2017 11:37:23 +0000 From: Bin Cheng To: "gcc-patches@gcc.gnu.org" CC: nd Subject: [PATCH PR81228]Fixes ICE by adding LTGT in vec_cmp. Date: Fri, 28 Jul 2017 11:37:22 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Bin.Cheng@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB5PR0801MB2741; 7:ogvIhTRPtZWxcijt8u8ux2/HVbBVzxnswZH8pZxqEDE1JUh2JmdRJ38rASmtMq5b98Njdo7g5GlS3Oaz3OeKdKac3+/4RN/hp1wie7okGhZ5Ek4ssHbchK52iGcr9+SK2++ypXlAhOQRM7Dcc2dHR/gEQRMW4+T4TQFsKpQ2nU7o9N0RXvrAec9tcKCt1o6HvVyPmMngTSajCurVSpVJg68zzoEv+qjuqJO1NBkuzANDKF3Kds0VZq2s33jv/ARF1vuW6mbbuCJj0QLRJG3F3mAgXkBeXJG5Izxz+5S3LmLr/i6GZYqhQNFWpAAVG0SE7MWdnkCq55zd+wnKXEIF0NXXSNOK29bNPh+ulpxRh8d3teeBRh65u31nzxYIYgEVRBzQwwDfspHKRgR8GN3KETofsXD03sFCw8fdRkHMyh1M9TAfb5Do1mn3a7kaAr8EKul11hFuN5YYpG8lF6Dbb0MEusQ9aahHodFOnLxNjzPkbzDugCpTtwE9NKIekGd16zXIEO7KVFZebJprTOFo+6g/n4aOJ7IVXwBDCsY8F8kHhEHT2d/iX8QUEgwkaHJZSggBXspBNVeY+oZzIYxZEOLATdESAwY2CkGLsex4GEBOzG8m4Jd6s8MRs6DuIDqZOMbWMePopDGGh7mxXcLMLuJLy0SY+6C6k6xpLQc+NivKzvDYu78WDa4Zv8buf52tdvs97r7mJsrLK3ILrqpWqzSwdxZoOjHpzTi7g84pzKW/VtRfDnwgmgy1apO1pFdLu6yynxidb4RjLnp9Euj/NwxJ5d6d9fTy/vl1bjjrpXY= x-ms-office365-filtering-correlation-id: 3b33b696-e427-4498-4f52-08d4d5ad0377 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254075)(48565401081)(300000503095)(300135400095)(2017052603031)(49563074)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:DB5PR0801MB2741; x-ms-traffictypediagnostic: DB5PR0801MB2741: nodisclaimer: True x-exchange-antispam-report-test: UriScan:(180628864354917); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(93006095)(93001095)(100000703101)(100105400095)(6055026)(6041248)(20161123562025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123564025)(20161123560025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DB5PR0801MB2741; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DB5PR0801MB2741; x-forefront-prvs: 03827AF76E x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39450400003)(39840400002)(39410400002)(39400400002)(39850400002)(199003)(54534003)(377424004)(189002)(6506006)(5640700003)(25786009)(5660300001)(7696004)(99286003)(101416001)(55016002)(2501003)(478600001)(9686003)(189998001)(97736004)(53936002)(4326008)(72206003)(38730400002)(86362001)(305945005)(105586002)(2906002)(6116002)(3846002)(81156014)(66066001)(68736007)(2351001)(8676002)(106356001)(74316002)(81166006)(7736002)(2900100001)(6916009)(110136004)(102836003)(77096006)(33656002)(6436002)(8936002)(50986999)(3660700001)(54356999)(3280700002)(99936001)(14454004); DIR:OUT; SFP:1101; SCL:1; SRVR:DB5PR0801MB2741; H:DB5PR0801MB2742.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jul 2017 11:37:22.8572 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR0801MB2741 X-IsSubscribed: yes Hi, This simple patch fixes the ICE by adding LTGT in vec_cmp pattern. I also modified the original test case into a compilation one since -fno-wrapping-math should not be used in general. Bootstrap and test on AArch64, test result check for x86_64. Is it OK? I would also need to backport it to gcc-7-branch. Thanks, bin 2017-07-27 Bin Cheng PR target/81228 * config/aarch64/aarch64-simd.md (vec_cmp): Add LTGT. gcc/testsuite/ChangeLog 2017-07-27 Bin Cheng PR target/81228 * gcc.dg/pr81228.c: New. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 011fcec0..9cd67a2 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2524,6 +2524,7 @@ case EQ: comparison = gen_aarch64_cmeq; break; + case LTGT: case UNEQ: case ORDERED: case UNORDERED: @@ -2571,6 +2572,7 @@ emit_insn (comparison (operands[0], operands[2], operands[3])); break; + case LTGT: case UNEQ: /* We first check (a > b || b > a) which is !UNEQ, inverting this result will then give us (a == b || a UNORDERED b). */ @@ -2578,7 +2580,8 @@ operands[2], operands[3])); emit_insn (gen_aarch64_cmgt (tmp, operands[3], operands[2])); emit_insn (gen_ior3 (operands[0], operands[0], tmp)); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); + if (code == UNEQ) + emit_insn (gen_one_cmpl2 (operands[0], operands[0])); break; case UNORDERED: diff --git a/gcc/testsuite/gcc.dg/pr81228.c b/gcc/testsuite/gcc.dg/pr81228.c new file mode 100644 index 0000000..3334299 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr81228.c @@ -0,0 +1,47 @@ +/* PR target/81228 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -fno-trapping-math" } */ +/* { dg-options "-O3 -fno-trapping-math -mavx" { target avx_runtime } } */ + +double s1[4], s2[4], s3[64]; + +int +main (void) +{ + int i; + asm volatile ("" : : : "memory"); + for (i = 0; i < 4; i++) + s3[0 * 4 + i] = __builtin_isgreater (s1[i], s2[i]) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[1 * 4 + i] = (!__builtin_isgreater (s1[i], s2[i])) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[2 * 4 + i] = __builtin_isgreaterequal (s1[i], s2[i]) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[3 * 4 + i] = (!__builtin_isgreaterequal (s1[i], s2[i])) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[4 * 4 + i] = __builtin_isless (s1[i], s2[i]) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[5 * 4 + i] = (!__builtin_isless (s1[i], s2[i])) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[6 * 4 + i] = __builtin_islessequal (s1[i], s2[i]) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[7 * 4 + i] = (!__builtin_islessequal (s1[i], s2[i])) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[8 * 4 + i] = __builtin_islessgreater (s1[i], s2[i]) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[9 * 4 + i] = (!__builtin_islessgreater (s1[i], s2[i])) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[10 * 4 + i] = __builtin_isunordered (s1[i], s2[i]) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[11 * 4 + i] = (!__builtin_isunordered (s1[i], s2[i])) ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[12 * 4 + i] = s1[i] > s2[i] ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[13 * 4 + i] = s1[i] >= s2[i] ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[14 * 4 + i] = s1[i] < s2[i] ? -1.0 : 0.0; + for (i = 0; i < 4; i++) + s3[15 * 4 + i] = s1[i] <= s2[i] ? -1.0 : 0.0; + asm volatile ("" : : : "memory"); + return 0; +}