| Message ID | CO2PR07MB2694F153A769D9F2E51D7CEB83270@CO2PR07MB2694.namprd07.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
Hi Naveen, On 15/03/17 05:32, Hurugalawadi, Naveen wrote: > Hi James, > >>> My reason for asking is that the instruction fusion implemented in LLVM >>> ( lib/Target/AArch64/AArch64MacroFusion.cpp::shouldScheduleAdjacent ) > Sorry. There seems to be some confusion in the branch instructions. > The branch should be conditional for ALU_BRANCH fusion. > > Please find attached the modified patch that fuses ALU instructions and > conditional branches. > > Bootstrapped and Regression tested on aarch64-thunder-linux. > Please review the patch and let us know if its okay? > > Thanks, > Naveen > + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) + && any_condjump_p (curr)) + { + /* These types correspond to the reservation "vulcan_alu_basic" for + Broadcom Vulcan: these are ALU operations that produce a single uop + during instruction decoding. */ The comment here still looks wrong. There is no vulcan_alu_basic reservation in any of the scheduling models. I suggest you reword the whole comment and not talk about particular CPUs, but rather about the kinds of instructions you want to fuse. If a reader wants to know which CPUs enable this fusion they should be looking at the CPU tuning structures rather than reading the comments here. Kyrill
diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def index f0e6dbc..300cd00 100644 --- a/gcc/config/aarch64/aarch64-fusion-pairs.def +++ b/gcc/config/aarch64/aarch64-fusion-pairs.def @@ -34,5 +34,6 @@ AARCH64_FUSION_PAIR ("movk+movk", MOVK_MOVK) AARCH64_FUSION_PAIR ("adrp+ldr", ADRP_LDR) AARCH64_FUSION_PAIR ("cmp+branch", CMP_BRANCH) AARCH64_FUSION_PAIR ("aes+aesmc", AES_AESMC) +AARCH64_FUSION_PAIR ("alu+branch", ALU_BRANCH) #undef AARCH64_FUSION_PAIR diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index a069427..f76a2ff 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -792,7 +792,8 @@ static const struct tune_params thunderx2t99_tunings = &generic_approx_modes, 4, /* memmov_cost. */ 4, /* issue_rate. */ - (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC), /* fusible_ops */ + (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC + | AARCH64_FUSE_ALU_BRANCH), /* fusible_ops */ 16, /* function_align. */ 8, /* jump_align. */ 16, /* loop_align. */ @@ -13981,6 +13982,37 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) return true; } + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) + && any_condjump_p (curr)) + { + /* These types correspond to the reservation "vulcan_alu_basic" for + Broadcom Vulcan: these are ALU operations that produce a single uop + during instruction decoding. */ + switch (get_attr_type (prev)) + { + case TYPE_ALU_IMM: + case TYPE_ALU_SREG: + case TYPE_ADC_REG: + case TYPE_ADC_IMM: + case TYPE_ADCS_REG: + case TYPE_ADCS_IMM: + case TYPE_LOGIC_REG: + case TYPE_LOGIC_IMM: + case TYPE_CSEL: + case TYPE_ADR: + case TYPE_MOV_IMM: + case TYPE_SHIFT_REG: + case TYPE_SHIFT_IMM: + case TYPE_BFM: + case TYPE_RBIT: + case TYPE_REV: + case TYPE_EXTEND: + return true; + + default:; + } + } + return false; }