| Message ID | CO2PR07MB2694DCE16B83432F033B76F7832C0@CO2PR07MB2694.namprd07.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Mar 06, 2017 at 05:09:34AM +0000, Hurugalawadi, Naveen wrote: > Hi, > > Please find attached the patch that adds "crypto_pmull" for AArch64. > > Bootstrapped and Regression tested on aarch64-thunder-linux. > > Please review the patch and let us know if its okay for Stage-1? > > Thanks, > Naveen > > 2017-03-06 Julian Brown <julian@codesourcery.com> > Naveen H.S <Naveen.Hurugalawadi@cavium.com> > > * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi) > (aarch64_crypto_pmullv2di): Change type attribute to crypto_pmull. > * config/aarch64/thunderx2t99.md (thunderx2t99_pmull): New > reservation. > * config/arm/cortex-a57.md (cortex_a57_neon_type): Add crypto_pmull to > attribute type list for neon_multiply. You need to do this for all cores which might be affected by this change, i.e. all those which model neon_mul_d_long. I see: gcc/config/arm/cortex-a53.md gcc/config/arm/exynos-m1.md Which your patch doesn't touch, but which have modeling for neon_mul_d_long. Thanks, James > * config/arm/crypto.md (crypto_vmullp64): Change type to crypto_pmull. > * config/arm/types.md (crypto_pmull): Add. > * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to > attribute type list.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b61f79a..338b9f8 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5818,7 +5818,7 @@ UNSPEC_PMULL))] "TARGET_SIMD && TARGET_CRYPTO" "pmull\\t%0.1q, %1.1d, %2.1d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "aarch64_crypto_pmullv2di" @@ -5828,5 +5828,5 @@ UNSPEC_PMULL2))] "TARGET_SIMD && TARGET_CRYPTO" "pmull2\\t%0.1q, %1.2d, %2.2d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index 0dd7199..67011ac 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -441,3 +441,8 @@ (and (eq_attr "tune" "thunderx2t99") (eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q")) "thunderx2t99_ls01,thunderx2t99_f01") + +(define_insn_reservation "thunderx2t99_pmull" 5 + (and (eq_attr "tune" "thunderx2t99") + (eq_attr "type" "crypto_pmull")) + "thunderx2t99_f1") diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index fd30758..ebf4a49 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -76,7 +76,7 @@ neon_mul_h_scalar_long, neon_mul_s_scalar_long,\ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long") + neon_sat_mul_s_scalar_long, crypto_pmull") (const_string "neon_multiply") (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\ neon_mul_h_scalar_q, neon_mul_s_scalar_q,\ diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index 46b0715..a5e558b 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -81,7 +81,7 @@ UNSPEC_VMULLP64))] "TARGET_CRYPTO" "vmull.p64\\t%q0, %P1, %P2" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "crypto_<crypto_pattern>" diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index b0b375c..253f496 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -539,6 +539,7 @@ ; crypto_sha1_slow ; crypto_sha256_fast ; crypto_sha256_slow +; crypto_pmull ; ; The classification below is for coprocessor instructions ; @@ -1078,6 +1079,7 @@ crypto_sha1_slow,\ crypto_sha256_fast,\ crypto_sha256_slow,\ + crypto_pmull,\ coproc" (const_string "untyped")) diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index 62a0732..34a13f4 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -527,5 +527,6 @@ (define_insn_reservation "xgene1_neon_pmull" 5 (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_mul_d_long,\ - ")) + crypto_pmull,\ + ")) "xgene1_decode2op")