From patchwork Mon Mar 27 04:57:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hurugalawadi, Naveen" X-Patchwork-Id: 743606 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vs1ws2Zr8z9s2s for ; Mon, 27 Mar 2017 15:57:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="yYf4ZY6C"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; q=dns; s=default; b=W+P7j8mB0Ap8GU1m 4AnwjOcnuVb9r0XufLuSZicecD7INwEGN3OsS4/cHc3I2145lHuOjHv5CeAPnGMt U2JJRYWIZt7QHQUvFTck/l/80UjU0kIpaa1CyLQlGt/HaLjMvCnHqWQUpFhLYtKP Evkdpfq0cBWQ2Uw9MImqUQLVRr4= DKIM-Signature: v=1; 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Mon, 27 Mar 2017 04:57:07 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com (10.166.214.7) by CO2PR07MB2615.namprd07.prod.outlook.com (10.166.213.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.991.14; Mon, 27 Mar 2017 04:57:06 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) by CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) with mapi id 15.01.0991.017; Mon, 27 Mar 2017 04:57:04 +0000 From: "Hurugalawadi, Naveen" To: Wilco Dijkstra , "Pinski, Andrew" CC: Kyrylo Tkachov , James Greenhalgh , nd , GCC Patches Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion Date: Mon, 27 Mar 2017 04:57:04 +0000 Message-ID: References: , In-Reply-To: authentication-results: arm.com; dkim=none (message not signed) header.d=none; arm.com; dmarc=none action=none header.from=cavium.com; x-microsoft-exchange-diagnostics: 1; CO2PR07MB2615; 7:GOUhrzWDtbViATTvzPBNZG7nAuwcV3upXYcEMsWxbjDEUCz4KWauhMB6Vf5pbqT6oA765POoN1aNM3n4E/ROE+NWKH+pWV3sxS63mea5Q0On0ULhakq2uCEaz3M70RrrfHKnwP6A6JbwaAftB7PF1Ysh5KHanQ2PaH6heawt6nNB578I7yNxdAy1z5V7YG3rdby3IyRrhwTHrtbQ62wLoPjiDs5owgYCQPQL+VZBv/bB+pxNEC8t8bKWQtGYWaaD7Y7scmseVrPPdmPQxjRVMnrlqoa12WbTlsXFPT34stT/ByVHTBQSaRx4M9YTdZXRfZ4aG6w+2GgjO78yS41tKA== x-forefront-antispam-report: SFV:SKI; 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SRVR:CO2PR07MB2615; BCL:0; PCL:0; RULEID:; SRVR:CO2PR07MB2615; x-forefront-prvs: 02596AB7DA spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2017 04:57:04.7538 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR07MB2615 Hi, Thanks for the review and suggestions. > I think the patch isn't quite complete yet. You will also need changes in > generic code. Currently sched_macro_fuse_insns() does: Modified the sched_macro_fuse_insns() as required. > Basically the idea is to push the check for CC usage into target macros Done. Pushed the check into target macros. The modifications were generic and and quite different from ALU+BRANCH fusion; a separate patch is posted with the above 2 modifications at:- https://gcc.gnu.org/ml/gcc-patches/2017-03/msg01368.html > Also in aarch64.c's macro fusion you need check that the branch >> instruction uses the same register Added to check that same registers are used in ALU and Branch instruction. Bootstrapped and Regression tested on AArch64. Please review the patch and let us know if its okay? Thanks, Naveen diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def index f0e6dbc..300cd00 100644 --- a/gcc/config/aarch64/aarch64-fusion-pairs.def +++ b/gcc/config/aarch64/aarch64-fusion-pairs.def @@ -34,5 +34,6 @@ AARCH64_FUSION_PAIR ("movk+movk", MOVK_MOVK) AARCH64_FUSION_PAIR ("adrp+ldr", ADRP_LDR) AARCH64_FUSION_PAIR ("cmp+branch", CMP_BRANCH) AARCH64_FUSION_PAIR ("aes+aesmc", AES_AESMC) +AARCH64_FUSION_PAIR ("alu+branch", ALU_BRANCH) #undef AARCH64_FUSION_PAIR diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 4f769a4..31bc5f4 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -792,7 +792,8 @@ static const struct tune_params thunderx2t99_tunings = &generic_approx_modes, 4, /* memmov_cost. */ 4, /* issue_rate. */ - (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC), /* fusible_ops */ + (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC + | AARCH64_FUSE_ALU_BRANCH), /* fusible_ops */ 16, /* function_align. */ 8, /* jump_align. */ 16, /* loop_align. */ @@ -13981,6 +13982,50 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) return true; } + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) + && any_condjump_p (curr)) + { + /* We're trying to match: + prev (alu_insn) == (set (r0) plus ((r0) (r1/imm))) + curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0) + (const_int 0)) + (label_ref ("SYM")) + (pc)) */ + + if (SET_DEST (curr_set) != (pc_rtx) + || GET_CODE (SET_SRC (curr_set)) != IF_THEN_ELSE + || ! REG_P (XEXP (XEXP (SET_SRC (curr_set), 0), 0)) + || ! REG_P (SET_DEST (prev_set)) + || REGNO (SET_DEST (prev_set)) + != REGNO (XEXP (XEXP (SET_SRC (curr_set), 0), 0))) + return false; + + /* Fuse ALU operations followed by conditional branch instruction. */ + switch (get_attr_type (prev)) + { + case TYPE_ALU_IMM: + case TYPE_ALU_SREG: + case TYPE_ADC_REG: + case TYPE_ADC_IMM: + case TYPE_ADCS_REG: + case TYPE_ADCS_IMM: + case TYPE_LOGIC_REG: + case TYPE_LOGIC_IMM: + case TYPE_CSEL: + case TYPE_ADR: + case TYPE_MOV_IMM: + case TYPE_SHIFT_REG: + case TYPE_SHIFT_IMM: + case TYPE_BFM: + case TYPE_RBIT: + case TYPE_REV: + case TYPE_EXTEND: + return true; + + default:; + } + } + return false; }