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[AArch64] Fix type for 1-element load

Message ID CO2PR07MB269471961F4D4E1D1ADB98AC832C0@CO2PR07MB2694.namprd07.prod.outlook.com
State New
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Commit Message

Hurugalawadi, Naveen March 6, 2017, 5:09 a.m. UTC
Hi,

Please find attached the patch that fixes type for 1-element load in AArch64.

Bootstrapped and Regression tested on aarch64-thunder-linux.
Please review the patch and let us know if its okay for Stage-1?

Thanks,
Naveen

2017-03-06  Julian Brown  <julian@codesourcery.com>
	    Naveen H.S  <Naveen.Hurugalawadi@cavium.com>

	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Fix
	type for 1-element load.

Comments

James Greenhalgh March 8, 2017, 5:37 p.m. UTC | #1
On Mon, Mar 06, 2017 at 05:09:51AM +0000, Hurugalawadi, Naveen wrote:
> Hi,
> 
> Please find attached the patch that fixes type for 1-element load in AArch64.
> 
> Bootstrapped and Regression tested on aarch64-thunder-linux.
> Please review the patch and let us know if its okay for Stage-1?
> 
> Thanks,
> Naveen
> 
> 2017-03-06  Julian Brown  <julian@codesourcery.com>
> 	    Naveen H.S  <Naveen.Hurugalawadi@cavium.com>
> 
> 	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Fix
> 	type for 1-element load.

OK.

Thanks,
James

> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
> index 878f86a..0443a86 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -561,7 +561,7 @@
>  	gcc_unreachable ();
>       }
>    }
> -  [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_1reg<q>")]
> +  [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_one_lane<q>")]
>  )
>  
>  (define_insn "*aarch64_simd_vec_copy_lane<mode>"
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 878f86a..0443a86 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -561,7 +561,7 @@ 
 	gcc_unreachable ();
      }
   }
-  [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_1reg<q>")]
+  [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_one_lane<q>")]
 )
 
 (define_insn "*aarch64_simd_vec_copy_lane<mode>"