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Tue, 25 Jul 2017 11:40:38 +0000 From: "Hurugalawadi, Naveen" To: James Greenhalgh CC: "gcc-patches@gcc.gnu.org" , Richard Earnshaw , Marcus Shawcroft , "nd@arm.com" , "Pinski, Andrew" Subject: Re: [PATCH][AArch64] vec_pack_trunc_ should split after register allocator Date: Tue, 25 Jul 2017 11:40:37 +0000 Message-ID: References: <20170721164242.GA8905@arm.com> , <20170725085728.GA26092@arm.com> In-Reply-To: <20170725085728.GA26092@arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Naveen.Hurugalawadi@cavium.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BN6PR07MB3411; 7:93p2c4ONJ2dblbxVjEMuIkSF1oKx3HvWGkFJTZGA+KlUvqfxuqwcP9Pc4JX9N+GnC0rVa4IAHEUWz34g2oXNBTWH6mA/Uaubc8rEB4L6ujtOO7lTiFBWTG9FKxhR4GcWYa/7YzStu/JVnLnBNtBIcTjqoreW3yz4icCPgwO72qIfSFN3XA1nvIVc4hj4Dag0xai2N7UC82PK8tZR7B1CH/za6wlf8qTWbqR7qhaLLHm70qYzFqxbISMkgAW5U1FwMq0iu2gczJJg/Ax7u3KCtb45ajcQNI3QAg/VPs5fto2B0GXuDYmbLNEJhsIl3Cy18ZJKpVymH1W2N/IdLlfCUlxfzJ/VYeoW66+D3FD9LmPTdRIzJjGmcHN7dpENKV936bCVTtI6SQ5cvP6oDhW0PImoBs2BMT3LcMWcUNS3Lhl4XcWATBBXNvJeyn0snxgjnQFaps6puSBXtOoLMXLgdVK06YAgdT6+AXfTmryzUFcoK/2iRHFHP6jIBPNIUZo6+9NHq+T0QFOveCkxbQLp5RIamRQOkGueXMg7HWM9PW+T7QYoZYPa0UnYZaoiH0cHNV1pU1Bo32nD7ACqqjtCAdnlcuDSS8pmo6ZQRObzQREyfQH/jfj3RouLZuyoxSaOlE8/sYm//ataUs4rMDSKXXZbBoCsB6+x7ETmbM3J5DKTUmi5oqBJDfg5YbthojG56M6Dz1KbKMOTYzL/SAYMOV534zY3Z6AMknLRif1QA5lIA/zNY2RVSwbikx31TAzeogoxrZNGvX0rjWvDIJ458Rakb7dmAtXtTivtsi+WLM4= x-forefront-antispam-report: SFV:SKI; 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SRVR:BN6PR07MB3411; x-ms-traffictypediagnostic: BN6PR07MB3411: x-exchange-antispam-report-test: UriScan:; x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(93006095)(93001095)(100000703101)(100105400095)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123558100)(20161123562025)(20161123560025)(20161123555025)(20161123564025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:BN6PR07MB3411; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:BN6PR07MB3411; x-forefront-prvs: 03793408BA received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Jul 2017 11:40:37.8152 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR07MB3411 Hi, >> I haven't been clear in what I was asking for Sorry. We understood right with the first comment but the second part confused us a bit :). >> Could you switch this back to an insn_and_split as it was in the previous >> patch, and just drop the && reload_completed ? Done. Bootstrapped and Regression done on AArch64-Thunder-Linux. Please review the patch and let me know if its okay? Thanks, Naveen diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 1cb6eeb..0011040 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1291,6 +1291,18 @@ [(set_attr "type" "neon_shift_imm_narrow_q")] ) +(define_insn "aarch64_simd_vec_pack_trunc_hi_" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (truncate: (match_operand:VQN 1 "register_operand" "w")) + (vec_select: + (match_operand: 3 "register_operand" "0") + (match_operand: 2 "vect_par_cnst_hi_half" ""))))] + "TARGET_SIMD" + "xtn2\\t%0., %1." + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + (define_expand "vec_pack_trunc_" [(match_operand: 0 "register_operand" "") (match_operand:VDN 1 "register_operand" "") @@ -1309,17 +1321,41 @@ ;; For quads. -(define_insn "vec_pack_trunc_" +(define_insn_and_split "vec_pack_trunc_" [(set (match_operand: 0 "register_operand" "=&w") (vec_concat: (truncate: (match_operand:VQN 1 "register_operand" "w")) (truncate: (match_operand:VQN 2 "register_operand" "w"))))] "TARGET_SIMD" + "#" + "" + [(const_int 0)] { if (BYTES_BIG_ENDIAN) - return "xtn\\t%0., %2.\;xtn2\\t%0., %1."; + { + rtx low_part = gen_lowpart (mode, operands[0]); + emit_insn (gen_aarch64_simd_vec_pack_trunc_ (low_part, + operands[2])); + rtx high_part = aarch64_simd_vect_par_cnst_half (mode, + true); + emit_insn (gen_aarch64_simd_vec_pack_trunc_hi_ (operands[0], + operands[1], + high_part, + operands[0])); + } else - return "xtn\\t%0., %1.\;xtn2\\t%0., %2."; + { + rtx low_part = gen_lowpart (mode, operands[0]); + emit_insn (gen_aarch64_simd_vec_pack_trunc_ (low_part, + operands[1])); + rtx high_part = aarch64_simd_vect_par_cnst_half (mode, + true); + emit_insn (gen_aarch64_simd_vec_pack_trunc_hi_ (operands[0], + operands[2], + high_part, + operands[0])); + } + DONE; } [(set_attr "type" "multiple") (set_attr "length" "8")]