From patchwork Wed Jun 4 21:23:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evgeny Stupachenko X-Patchwork-Id: 356105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 89D87140091 for ; Thu, 5 Jun 2014 07:24:10 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=dLMWeu9rpSC+EaTmIP tBcYLC0tB5EO8E9dWSvtv3oojpcMx6N8rW+41r4m0SMpxrKd1cA2fxiL85g7zqAc aRIakbU098T9hqv3f3XPC3MPZXEOfAaqJKZT8P5/shxwwlwulnUoPn9iYGWBmqEH 5FbLa+8O2TolthiomW5i9bvK4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=YfyGlssZAlxzDulRTra2rvKj Ag8=; b=b64INCOizyeqbuq04ub9+9MxQ+eIV3Ikkb+TLnrqkzbcNBSA5GIXAEBg UbRlXOP2inXP4U5f3nYPj532dn6lVVbxIsdC4oYgKv50/9YnnIhOuQ4Kc35XVgvT FK102be37vGvrPECkqvvzCYW0nZ/BSIrsCA2JQNviqRiSIYq1yQ= Received: (qmail 10026 invoked by alias); 4 Jun 2014 21:24:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10014 invoked by uid 89); 4 Jun 2014 21:24:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f170.google.com Received: from mail-ob0-f170.google.com (HELO mail-ob0-f170.google.com) (209.85.214.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 04 Jun 2014 21:24:01 +0000 Received: by mail-ob0-f170.google.com with SMTP id uy5so109115obc.15 for ; Wed, 04 Jun 2014 14:24:00 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.231.134 with SMTP id tg6mr15788361oec.84.1401917040032; Wed, 04 Jun 2014 14:24:00 -0700 (PDT) Received: by 10.76.18.209 with HTTP; Wed, 4 Jun 2014 14:23:59 -0700 (PDT) In-Reply-To: <538F6DCC.5000402@redhat.com> References: <535FBC20.1000400@redhat.com> <535FE3CF.2020005@redhat.com> <537A2A91.3000809@redhat.com> <538F6DCC.5000402@redhat.com> Date: Thu, 5 Jun 2014 01:23:59 +0400 Message-ID: Subject: Re: [PATCH 2/2, x86] Add palignr support for AVX2. From: Evgeny Stupachenko To: Richard Henderson Cc: GCC Patches , Richard Biener , Uros Bizjak , "H.J. Lu" X-IsSubscribed: yes Thanks. Moving pattern down helps. Now make check for the following patch passed: On Wed, Jun 4, 2014 at 11:04 PM, Richard Henderson wrote: > On 06/04/2014 10:06 AM, Evgeny Stupachenko wrote: >> Is it ok to use the following pattern? >> >> patch passed bootstrap and make check, but one test failed: >> gcc/testsuite/gcc.target/i386/vect-rebuild.c >> It failed on /* { dg-final { scan-assembler-times "\tv?permilpd\[ \t\]" 1 } } */ >> which is now palignr. However, both palignr and permilpd costs 1 tick >> and take 6 bytes in the opcode. >> I vote for modifying the test to scan for palignr: >> /* { dg-final { scan-assembler-times "\tv?palignr\[ \t\]" 1 } } */ >> >> 2014-06-04 Evgeny Stupachenko >> >> * config/i386/sse.md (*ssse3_palignr_perm): New. >> * config/i386/predicates.md (palignr_operand): New. >> Indicates if permutation is suitable for palignr instruction. > > Surely permilpd avoids some sort of reformatting penalty when actually using > doubles. > > If you move this pattern down below the other vec_select patterns, we'll prefer > the others for matching masks. > > > r~ diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 2ef1384..8266f3e 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1417,6 +1417,22 @@ return true; }) +;; Return true if OP is a parallel for a palignr permute. +(define_predicate "palignr_operand" + (and (match_code "parallel") + (match_code "const_int" "a")) +{ + int elt = INTVAL (XVECEXP (op, 0, 0)); + int i, nelt = XVECLEN (op, 0); + + /* Check that an order in the permutation is suitable for palignr. + For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */ + for (i = 1; i < nelt; ++i) + if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt)) + return false; + return true; +}) + ;; Return true if OP is a proper third operand to vpblendw256. (define_predicate "avx2_pblendw_operand" (match_code "const_int") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c91626b..d907353 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14551,6 +14551,35 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) +(define_insn "*ssse3_palignr_perm" + [(set (match_operand:V_128 0 "register_operand" "=x,x") + (vec_select:V_128 + (match_operand:V_128 1 "register_operand" "0,x") + (match_parallel 2 "palignr_operand" + [(match_operand 3 "const_int_operand" "n, n")])))] + "TARGET_SSSE3" +{ + enum machine_mode imode = GET_MODE_INNER (GET_MODE (operands[0])); + operands[2] = GEN_INT (INTVAL (operands[3]) * GET_MODE_SIZE (imode)); + + switch (which_alternative) + { + case 0: + return "palignr\t{%2, %1, %0|%0, %1, %2}"; + case 1: + return "vpalignr\t{%2, %1, %1, %0|%0, %1, %1, %2}"; + default: + gcc_unreachable (); + } +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sseishft") + (set_attr "atom_unit" "sishuf") + (set_attr "prefix_data16" "1,*") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,vex")]) + (define_expand "avx_vinsertf128" [(match_operand:V_256 0 "register_operand") (match_operand:V_256 1 "register_operand")