From patchwork Mon Oct 13 15:17:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Evgeny Stupachenko X-Patchwork-Id: 399220 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D4E6914007B for ; Tue, 14 Oct 2014 02:17:19 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type:content-transfer-encoding; q=dns; s= default; b=RkzD6BU+I46mWJ20MzfeMtrfxvXpg/6O/UChiWsFUp/SrOTkUFXEx ZDgtSMJBADnPqGwBI1QugByT/hKlyhjeJ3IDxsgbtA1t3/hkezZ81bVjcv1wzdQC esgvoBU5RIopx0y2s4vosmbDBhIU/W9Wjenu8F5h7TBGHzpHQ3ZGH4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type:content-transfer-encoding; s=default; bh=lazvGJPpuSVLz6sCRht7RW92BGo=; b=BWQPMMzqEsuzxiaS57H8PQPuMt5b c4oGL3fpCA9BWyDGpAnt92i4qWUb7xJ3mBLcvDhzOgLIyQx0AtQw2xQVY7A/6RFh atPMsIncGYsDohNg+XOJOWE3gwdf1PfRyOjFvN/QNBcm/TxoeDC1lWrTfhb9kx3y xrbcj7lEQAqkZeA= Received: (qmail 30950 invoked by alias); 13 Oct 2014 15:17:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30936 invoked by uid 89); 13 Oct 2014 15:17:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ig0-f175.google.com Received: from mail-ig0-f175.google.com (HELO mail-ig0-f175.google.com) (209.85.213.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 13 Oct 2014 15:17:11 +0000 Received: by mail-ig0-f175.google.com with SMTP id uq10so10778703igb.14 for ; Mon, 13 Oct 2014 08:17:09 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.50.43.130 with SMTP id w2mr2231669igl.34.1413213428853; Mon, 13 Oct 2014 08:17:08 -0700 (PDT) Received: by 10.107.6.95 with HTTP; Mon, 13 Oct 2014 08:17:08 -0700 (PDT) In-Reply-To: References: Date: Mon, 13 Oct 2014 19:17:08 +0400 Message-ID: Subject: Re: [PATCH 3/X, i386, PR54232] Enable EBX for x86 in 32bits PIC code From: Evgeny Stupachenko To: Uros Bizjak Cc: Jeff Law , Vladimir Makarov , GCC Patches X-IsSubscribed: yes Patch updated with the comment: cost++; On Fri, Oct 10, 2014 at 3:04 PM, Uros Bizjak wrote: > On Fri, Oct 10, 2014 at 9:58 AM, Evgeny Stupachenko wrote: >> the patch improves performance when previous are applied. >> It makes RTL loop invariant behavior for GOT loads same as it was >> before the 2 previous patches. > >> The patch fixes x86 address cost so that cost for addresses with GOT >> register becomes less, how it was before enabling EBX. >> >> In x86_address_cost the result of “REGNO (parts.base) >= >> FIRST_PSEUDO_REGISTER” for hard ebx was always false. The patch makes >> condition result >> the same when parts.base is GOT register (the same for parts.index). >> >> 2014-10-08 Evgeny Stupachenko >> * gcc/config/i386/i386.c (ix86_address_cost): Lower cost for >> when address contains GOT register. >> >> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c >> index b43e870..9d8cfd1 100644 >> --- a/gcc/config/i386/i386.c >> +++ b/gcc/config/i386/i386.c >> @@ -12497,8 +12497,12 @@ ix86_address_cost (rtx x, enum machine_mode, >> addr_space_t, bool) >> cost++; > > Please add a short comment here, explaining the reason for new condition. > >> if (parts.base >> + && (!pic_offset_table_rtx >> + || REGNO (pic_offset_table_rtx) != REGNO(parts.base)) >> && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER) >> && parts.index >> + && (!pic_offset_table_rtx >> + || REGNO (pic_offset_table_rtx) != REGNO(parts.index)) >> && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER) >> && parts.base != parts.index) >> cost++; > > Otherwise LGTM, but please repost the patch with a comment. > > Uros. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 2a64d2d..5fd6a82 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -12455,9 +12455,18 @@ ix86_address_cost (rtx x, enum machine_mode, addr_space_t, bool) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER))) cost++; + /* When address base or index is "pic_offset_table_rtx" we don't increase + address cost. When a memop with "pic_offset_table_rtx" is not invariant + itself it most likely means that base or index is not invariant. + Therefore only "pic_offset_table_rtx" could be hoisted out, which is not + profitable for x86. */ if (parts.base + && (!pic_offset_table_rtx + || REGNO (pic_offset_table_rtx) != REGNO(parts.base)) && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER) && parts.index + && (!pic_offset_table_rtx + || REGNO (pic_offset_table_rtx) != REGNO(parts.index)) && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER) && parts.base != parts.index)