From patchwork Sat Jun 4 06:35:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Virendra Pathak X-Patchwork-Id: 630139 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rMB7s3Rf2z9sD5 for ; Sat, 4 Jun 2016 16:36:40 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=biaB8BHF; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=mMm0Qswyirp7aH5QeXFdIx84acrQMqNEUszLjkA9C0P fd/2JKqeGbkEYkOpeFYqW6+4PsXld+IZvYRqCcbLPbAo1VEzpa9i6O+A3ofBUcj9 1jYnVXsy6Imh3vuKF0TU4NDEIKbymPLS0HKc8EDP55cGB4vh5IUvDPHNjDFtyW1Y = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=UhvlmM6/92IgxHi5Ej9pwGHgWeI=; b=biaB8BHFaeUAoTvux /uhGkHB6u2n6TR93xzfxx6lNIQ2KvqLQ1QaWo+URfJPEkmlUN45NFNW1bjBhY2jF RdmnFnYWvZFMI0TyO5RBJQ/jrNJZhYMj1n2AhclMFcu3NsURY3FqulFewr+lxQR/ DEGDHLxzCvl+sFgW84P7OP9H3k= Received: (qmail 93989 invoked by alias); 4 Jun 2016 06:36:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 93955 invoked by uid 89); 4 Jun 2016 06:36:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=aarch64_tune, company, kindly X-HELO: mail-io0-f169.google.com Received: from mail-io0-f169.google.com (HELO mail-io0-f169.google.com) (209.85.223.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Sat, 04 Jun 2016 06:36:19 +0000 Received: by mail-io0-f169.google.com with SMTP id o189so90536919ioe.2 for ; Fri, 03 Jun 2016 23:36:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=tZ3GOPI8uyUTNg9KTeoCf5SCxG8ylXob5PtDtFInISc=; b=K1UM9YWmcUhwU09Vq1mWAjj8/RckLyqVVOT3NYwRuDvtDx6i59fB3nlPumPX2Are8i YDfSsg+FIZ97RKRoaTWPDIDvSIFj5FdIS64OPNTPLCXgaQIC6N5Yl8Am4yULprngxG4W 8a8kEVAjz2kkaahylILCXBo5sYIl0AlutgXBMTrrafhSFPln5gqgT+YUuDZRqoNLSXLn NarkqUfBfrdfcBsV9DINuyZLC1PTVpJ0aUZz8smVU9m0vYJblSKwWQDd/FvFRLmI6XxA Cjeg/6+Fuk8Szr6D4ssNLhk+BabyC39II8ukdQOX5Jo+zRIsliclOisCBK7gSQ1MR44Q Ge0A== X-Gm-Message-State: ALyK8tKmAZgUIs4hYARxCo6gQhQf26N76fhPMz6ZRa33M3KP+n99Hdfnu0YPO8zmEy5n5mk6kl27IpOZV8vvroO0 X-Received: by 10.107.134.100 with SMTP id i97mr9664992iod.93.1465022177495; Fri, 03 Jun 2016 23:36:17 -0700 (PDT) MIME-Version: 1.0 Received: by 10.50.202.106 with HTTP; Fri, 3 Jun 2016 23:35:57 -0700 (PDT) From: Virendra Pathak Date: Sat, 4 Jun 2016 12:05:57 +0530 Message-ID: Subject: [PATCH/AARCH64] Add vulcan -mcpu support To: gcc-patches@gcc.gnu.org Cc: James.Greenhalgh@arm.com, Richard.Earnshaw@arm.com, Ramana.Radhakrishnan@arm.com, Marcus.Shawcroft@arm.com Hi gcc-patches group, Please find the basic patch for adding -mcpu=vulcan support in the gcc. Broadcom's vulcan is an armv8-a aarch64 based server processor. At present we are using schedule model of cortex-a57 but soon we will be submitting a schedule model for vulcan. Please review the patch (attached with this mail) and kindly merge it in the gcc-6-branch. Tested the patch with aarch64-linux-gnu cross build, aarch64-unknown-linux-gnu native build and make check. We have also obtained company wide agreement with FSF for contributing to gcc project. Thanks. ChangeLog: * config/aarch64/aarch64-cores.def (vulcan): New core * config/aarch64/aarch64-tune.md: Regenerate * doc/invoke.texi (AARCH64/mtune): Document vulcan as an available option. with regards, Virendra Pathak From 8d065016856606740a3928518ed6a3f9933fb130 Mon Sep 17 00:00:00 2001 From: Virendra Pathak Date: Wed, 1 Jun 2016 03:15:33 -0700 Subject: [PATCH] [AArch64] Add -mcpu vulcan support --- gcc/config/aarch64/aarch64-cores.def | 1 + gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/doc/invoke.texi | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 251a3eb..b0acad9 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -46,6 +46,7 @@ AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AA AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08") AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, "0x53", "0x001") AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x51", "0x800") +AARCH64_CORE("vulcan", vulcan, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x42", "0x516") AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, "0x43", "0x0a1") AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000") diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index cbc6f48..c758a5f 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53" + "cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,vulcan,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 821f8fd..146042d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12955,8 +12955,8 @@ processors implementing the target architecture. Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, -@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx}, -@samp{xgene1}. +@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{vulcan}, +@samp{thunderx}, @samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible values for this