From patchwork Fri Sep 23 11:11:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dinar Temirbulatov X-Patchwork-Id: 116041 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D24A0B6F7E for ; Fri, 23 Sep 2011 21:11:35 +1000 (EST) Received: (qmail 31813 invoked by alias); 23 Sep 2011 11:11:32 -0000 Received: (qmail 31800 invoked by uid 22791); 23 Sep 2011 11:11:30 -0000 X-SWARE-Spam-Status: No, hits=-0.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-iy0-f175.google.com (HELO mail-iy0-f175.google.com) (209.85.210.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 23 Sep 2011 11:11:15 +0000 Received: by iadx2 with SMTP id x2so4487412iad.20 for ; Fri, 23 Sep 2011 04:11:15 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.25.206 with SMTP id a14mr2981543ibc.15.1316776274877; Fri, 23 Sep 2011 04:11:14 -0700 (PDT) Received: by 10.231.79.135 with HTTP; Fri, 23 Sep 2011 04:11:14 -0700 (PDT) In-Reply-To: References: Date: Fri, 23 Sep 2011 15:11:14 +0400 Message-ID: Subject: Re: MIPS Fix PR18141 From: Dinar Temirbulatov To: rdsandiford@googlemail.com Cc: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org hi, Richard, This version of patch showed no regressions on mipsel-unknown-linux-gnu. Thanks, Dinar. On Wed, Sep 21, 2011 at 4:59 PM, Richard Sandiford wrote: > Dinar Temirbulatov writes: >> @@ -14696,7 +14696,11 @@ mips_avoid_hazard (rtx after, rtx insn, >>       clobber hi and lo.  */ >>    if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) >>      nops = 2 - *hilo_delay; >> -  else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) >> +  else if ((*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) >> +         && !((GET_MODE (*delayed_reg) == DFmode && set_after != 0 >> +            && (set = single_set (insn)) != NULL_RTX && GET_MODE (SET_DEST(set)) == DFmode >> +            && XINT((XEXP (pattern, 1)), 1) == UNSPEC_LOAD_HIGH >> +            && XINT((XEXP (*set_after, 1)), 1) == UNSPEC_LOAD_LOW))) > > This isn't safe because the patterns might not be UNSPECs (so XINT (...) > would be meaningless).  It's better to check the insn code instead. > Something like: > >  else if (*delayed_reg != 0 >           && reg_referenced_p (*delayed_reg, pattern) >           && !(recog_memoized (insn) == CODE_FOR_load_highdf >                && recog_memoized (*set_after) == CODE_FOR_load_lowdf)) > > (untested).  Note that *set_after should always be nonnull if > *delayed_reg is. > > Looks good otherwise. > > Richard > diff -ruNp gcc-20110912-orig/gcc/config/mips/mips.c gcc-20110912-fixed/gcc/config/mips/mips.c --- gcc-20110912-orig/gcc/config/mips/mips.c 2011-09-12 17:22:27.576457121 +0400 +++ gcc-20110912-fixed/gcc/config/mips/mips.c 2011-09-23 14:24:45.379778834 +0400 @@ -14659,20 +14659,20 @@ mips_orphaned_high_part_p (htab_t htab, INSN and a previous instruction, avoid it by inserting nops after instruction AFTER. - *DELAYED_REG and *HILO_DELAY describe the hazards that apply at - this point. If *DELAYED_REG is non-null, INSN must wait a cycle - before using the value of that register. *HILO_DELAY counts the - number of instructions since the last hilo hazard (that is, - the number of instructions since the last MFLO or MFHI). + *DELAYED_REG, *SET_AFTER and *HILO_DELAY describe the hazards that + apply at this point. If *DELAYED_REG and *SET_AFTER is non-null, + INSN must wait a cycle before using the value of that register. + *HILO_DELAY counts the number of instructions since the last hilo hazard + (that is, the number of instructions since the last MFLO or MFHI). - After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY - for the next instruction. + After inserting nops for INSN, update *DELAYED_REG, *SET_AFTER + and *HILO_DELAY for the next instruction. LO_REG is an rtx for the LO register, used in dependence checking. */ static void mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay, - rtx *delayed_reg, rtx lo_reg) + rtx *delayed_reg, rtx lo_reg, rtx *set_after) { rtx pattern, set; int nops, ninsns; @@ -14696,7 +14696,9 @@ mips_avoid_hazard (rtx after, rtx insn, clobber hi and lo. */ if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) nops = 2 - *hilo_delay; - else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) + else if ((*delayed_reg != 0 && set_after != 0 && reg_referenced_p (*delayed_reg, pattern)) + && !(recog_memoized (insn) == CODE_FOR_load_highdf + && recog_memoized (*set_after) == CODE_FOR_load_lowdf)) nops = 1; else nops = 0; @@ -14710,6 +14712,7 @@ mips_avoid_hazard (rtx after, rtx insn, /* Set up the state for the next instruction. */ *hilo_delay += ninsns; *delayed_reg = 0; + *set_after = 0; if (INSN_CODE (insn) >= 0) switch (get_attr_hazard (insn)) { @@ -14724,6 +14727,7 @@ mips_avoid_hazard (rtx after, rtx insn, set = single_set (insn); gcc_assert (set); *delayed_reg = SET_DEST (set); + *set_after = insn; break; } } @@ -14736,7 +14740,7 @@ mips_avoid_hazard (rtx after, rtx insn, static void mips_reorg_process_insns (void) { - rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg; + rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg, set_after; int hilo_delay; htab_t htab; @@ -14811,7 +14815,7 @@ mips_reorg_process_insns (void) INSN_CODE (subinsn) = CODE_FOR_nop; } mips_avoid_hazard (last_insn, subinsn, &hilo_delay, - &delayed_reg, lo_reg); + &delayed_reg, lo_reg, &set_after); } last_insn = insn; } @@ -14832,7 +14836,7 @@ mips_reorg_process_insns (void) else { mips_avoid_hazard (last_insn, insn, &hilo_delay, - &delayed_reg, lo_reg); + &delayed_reg, lo_reg, &set_after); last_insn = insn; } }