From patchwork Mon Aug 10 19:20:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 505773 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1299B14016A for ; Tue, 11 Aug 2015 05:20:13 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=fUMxOrA3; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=lqmBjgmXv40eUVEjlP QJ2z25CHCKYrz5kj8ex2NzUNTmgKzUiLrx/66yKkt6mMVB/2IoeqgO9/JBoEzRUI YsNJL8pd+L4WRsHXRO34FtfkD6zrq/WpQh04I7oiUtPso/L5iuXPMPEY5kvurOlH yVNZHQBYWTjaDTJhvMiQrbKk4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=Xw6JZNmFxCv3NRBy57P+CUC3 E7s=; b=fUMxOrA3dN30aOhTT5dUMwUuL2665ZuTrSGeRKLAU9sSQBUY5RZw054M bbOX3rG/657NUrDDUtJxxeQFc4DLmIbqxPOIN0eW9Wl0nA0i7vrylxnR8bjLCz+R rOb5wv765goKj05viZjdncXh1FeqRfkT631NuN2yu9SVodrO84Q= Received: (qmail 119598 invoked by alias); 10 Aug 2015 19:20:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 119586 invoked by uid 89); 10 Aug 2015 19:20:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f169.google.com Received: from mail-ob0-f169.google.com (HELO mail-ob0-f169.google.com) (209.85.214.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 10 Aug 2015 19:20:04 +0000 Received: by obnw1 with SMTP id w1so131218423obn.3 for ; Mon, 10 Aug 2015 12:20:02 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.48.38 with SMTP id i6mr21884603oen.0.1439234402010; Mon, 10 Aug 2015 12:20:02 -0700 (PDT) Received: by 10.76.170.36 with HTTP; Mon, 10 Aug 2015 12:20:01 -0700 (PDT) In-Reply-To: References: <20150807225741.GA13944@intel.com> Date: Mon, 10 Aug 2015 12:20:01 -0700 Message-ID: Subject: Re: [PATCH] Treat model == 0x4f as Broadwell From: "H.J. Lu" To: Uros Bizjak Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes On Sat, Aug 8, 2015 at 12:42 AM, Uros Bizjak wrote: > On Sat, Aug 8, 2015 at 12:57 AM, H.J. Lu wrote: >> From Intel SDM Vol 3: >> >> Table 35-29 lists MSRs that are common to processors based on the >> Broadwell microarchitectures (including CPUID signatures 06_3DH, 06_47H, >> 06_4FH, and 06_56H). >> >> OK for trunk? > > These kind of patches fall into trivial category. They don't need approval.. > > Uros. I also checked in this. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 146a730..34a5c1a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-08-10 H.J. Lu + + * gcc.target/i386/builtin_target.c (check_intel_cpu_model): + Treat model == 0x4f as Broadwell. + 2015-08-10 Francois-Xavier Coudert PR libfortran/67140 diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c index 10c0568..4adea27 100644 --- a/gcc/testsuite/gcc.target/i386/builtin_target.c +++ b/gcc/testsuite/gcc.target/i386/builtin_target.c @@ -74,6 +74,7 @@ check_intel_cpu_model (unsigned int family, unsigned int model, assert (__builtin_cpu_is ("haswell")); break; case 0x3d: + case 0x47: case 0x4f: case 0x56: /* Broadwell. */ diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 79df462..95a10f2 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,8 @@ +2015-08-10 H.J. Lu + + * config/i386/cpuinfo.c (get_intel_cpu): Treat model == 0x4f as + Broadwell. + 2015-07-22 Uros Bizjak PR target/66954 diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c index 01dbb59..57711d0 100644 --- a/libgcc/config/i386/cpuinfo.c +++ b/libgcc/config/i386/cpuinfo.c @@ -232,6 +232,7 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id) __cpu_model.__cpu_subtype = INTEL_COREI7_HASWELL; break; case 0x3d: + case 0x47: case 0x4f: case 0x56: