From patchwork Thu Jul 21 16:13:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 106092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D1D22B6F68 for ; Fri, 22 Jul 2011 02:13:46 +1000 (EST) Received: (qmail 32551 invoked by alias); 21 Jul 2011 16:13:39 -0000 Received: (qmail 32537 invoked by uid 22791); 21 Jul 2011 16:13:38 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 21 Jul 2011 16:13:04 +0000 Received: by qwh5 with SMTP id 5so841645qwh.20 for ; Thu, 21 Jul 2011 09:13:03 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.43.231 with SMTP id x39mr370304qce.198.1311264783050; Thu, 21 Jul 2011 09:13:03 -0700 (PDT) Received: by 10.229.98.193 with HTTP; Thu, 21 Jul 2011 09:13:02 -0700 (PDT) In-Reply-To: <20110721040627.GA18628@intel.com> References: <20110721040627.GA18628@intel.com> Date: Thu, 21 Jul 2011 09:13:03 -0700 Message-ID: Subject: Re: PATCH [9/n] X32: PR target/49798: Zero-extend symbol address to 64bit if needed From: "H.J. Lu" To: Richard Henderson Cc: gcc-patches@gcc.gnu.org, Uros Bizjak X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Wed, Jul 20, 2011 at 9:06 PM, H.J. Lu wrote: > The testcase is gcc.c-torture/compile/pr45728.c.  This patch zero-extends > symbol address to 64bit if needd.  OK for trunk? > > Thanks. > > > H.J. > ---- > 2011-07-20  H.J. Lu   > >        PR target/49798 >        * config/i386/i386.c (ix86_asm_integer): New. >        (TARGET_ASM_INTEGER): Likewise. > This is the updated patch, using the same approach in sparc_assemble_integer. OK for trunk? Thanks. H.J. 2011-07-21 H.J. Lu PR target/49798 * config/i386/i386.c (ix86_asm_integer): New. (TARGET_ASM_INTEGER): Likewise. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a60085c..d72edff 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -14289,6 +14289,24 @@ i386_asm_output_addr_const_extra (FILE *file, rtx x) return true; } + +/* Implementation of TARGET_ASM_INTEGER. */ + +static bool +ix86_asm_integer (rtx x, unsigned int size, int aligned_p) +{ + if (TARGET_X32 + && size == 8 + && !CONST_INT_P (x) + && !CONST_DOUBLE_P (x)) + { + /* Zero-extend symbol address to 64bit. */ + default_assemble_integer (x, 4, aligned_p); + default_assemble_integer (const0_rtx, 4, aligned_p); + return true; + } + return default_assemble_integer (x, size, aligned_p); +} /* Split one or more double-mode RTL references into pairs of half-mode references. The RTL can be REG, offsettable MEM, integer constant, or @@ -34892,6 +34910,8 @@ ix86_autovectorize_vector_sizes (void) #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP #undef TARGET_ASM_UNALIGNED_DI_OP #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP +#undef TARGET_ASM_INTEGER +#define TARGET_ASM_INTEGER ix86_asm_integer #undef TARGET_PRINT_OPERAND #define TARGET_PRINT_OPERAND ix86_print_operand