From patchwork Sun Dec 6 19:10:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1411774 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=EG5Amtal; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CpwzC74dGz9s0b for ; Mon, 7 Dec 2020 06:11:34 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5989B3857C75; Sun, 6 Dec 2020 19:11:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5989B3857C75 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1607281888; bh=aot4LOI44vidMGIwZSiSc4yeyGI3Y3JSt1caxCKBuj0=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=EG5AmtalZ0czkSYD58U1fhBwBQNisgMbKdJfrZGbWloxoTYcJq3T3iqWUH8ZkYgsR gm9lBiHGqufMgL8lFiI/YRoYA112p8QEZGMFwuZ9fQ0rGOFHG/4n6YfSt15K1LsAUf DXfBRmKYNy+nkudABT1Z7mp2egBhw5kW5hsZ0iBs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x333.google.com (mail-ot1-x333.google.com [IPv6:2607:f8b0:4864:20::333]) by sourceware.org (Postfix) with ESMTPS id 8FE2C3857C46 for ; Sun, 6 Dec 2020 19:11:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 8FE2C3857C46 Received: by mail-ot1-x333.google.com with SMTP id o11so7874229ote.4 for ; Sun, 06 Dec 2020 11:11:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aot4LOI44vidMGIwZSiSc4yeyGI3Y3JSt1caxCKBuj0=; b=Dj++kujI26pbxfgQt/aFl8jJmPM9tIac37YPophzKtf0NfNA7vyKEolQrUhm9y1r/N HlqgyEfryBvq/MN5VAqVAqBkHtLpHbOIz4hxDlYWPG1D+14APgLKIfAWdlPOcVM4qHy7 B/3pC5KYYLId80tNLmHcvDzSnDqyrv44MQRn5nIWysPfTcF2LnOllsomRD8QgSO1LZgE KGw4R4KgfAVDcEA1Ebllx8JuZUn6KGYqlU00oZuTD+cRx7ynR3pp4dsI5Ph1RelWTQ5n kZkoNjs/WxgkGN5SYusBdS6z39qdKte45dT6tm1dZcveoCJpoRaAMJmefzNx+Ez3fVr+ B6jg== X-Gm-Message-State: AOAM532V5FIwhnmHNHD63yP14WayYBLHIUXXL7p94KKgMijzvuk/Xb6K Eeq7jBWKxsJi+AIaDXibsm8XvtDtafo+AuuviM8= X-Google-Smtp-Source: ABdhPJwrzaRSi6GX5QdbSsGMEVLXk9tEU60E7cCIchIwSaGnPClVGqNexgHFGK6PI9B5M4sfhKBeWMX+LvBXT8TzKPA= X-Received: by 2002:a05:6830:1213:: with SMTP id r19mr10742425otp.269.1607281884974; Sun, 06 Dec 2020 11:11:24 -0800 (PST) MIME-Version: 1.0 References: <20201206185101.937177-1-hjl.tools@gmail.com> In-Reply-To: Date: Sun, 6 Dec 2020 11:10:48 -0800 Message-ID: Subject: V2 [PATCH] x86: Check mode of pseudo register push To: Uros Bizjak X-Spam-Status: No, score=-3037.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" On Sun, Dec 6, 2020 at 10:59 AM Uros Bizjak wrote: > > On Sun, Dec 6, 2020 at 7:51 PM H.J. Lu wrote: > > > > commit 266f44a91c0c9705d3d18e82d7c5bab32927a18f > > Author: H.J. Lu > > Date: Sun May 17 10:10:34 2020 -0700 > > > > x86: Allow V1TI vector register pushes > > > > Add V1TI vector register push and split it after reload to a sequence > > of: > > > > (set (reg:P SP_REG) (plus:P SP_REG) (const_int -8))) > > (set (match_dup 0) (match_dup 1)) > > > > added a pseudo register push check. But > > > > (insn 13 12 14 3 (set (mem:SI (pre_dec:SI (reg/f:SI 7 sp)) [0 S4 A32]) > > (reg/v:SI 87 [ srclen ])) "x.c":37:16 54 {*pushsi2} > > (expr_list:REG_DEAD (reg/v:SI 87 [ srclen ]) > > (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) > > (nil)))) > > > > is not a pseudo register push. In 64-bit mode, mode of pseudo register > > push is TImode. In 32-bit mode, it is DImode. Add pseudo register push > > mode check to pseudo_reg_set. > > > > gcc/ > > > > PR target/98161 > > * config/i386/i386-features.c (pseudo_reg_set): Check mode of > > pseudo register push. > > > > gcc/testsuite/ > > > > * gcc.target/i386/pr98161.c: New test. > > --- > > gcc/config/i386/i386-features.c | 2 ++ > > gcc/testsuite/gcc.target/i386/pr98161.c | 48 +++++++++++++++++++++++++ > > 2 files changed, 50 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/i386/pr98161.c > > > > diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c > > index ff6676f54f7..8ac11b13ad2 100644 > > --- a/gcc/config/i386/i386-features.c > > +++ b/gcc/config/i386/i386-features.c > > @@ -1266,8 +1266,10 @@ pseudo_reg_set (rtx_insn *insn) > > return NULL; > > > > /* Check pseudo register push first. */ > > + machine_mode mode = TARGET_64BIT ? TImode : DImode; > > if (REG_P (SET_SRC (set)) > > && !HARD_REGISTER_P (SET_SRC (set)) > > + && GET_MODE (SET_DEST (set)) == mode > > && push_operand (SET_DEST (set), GET_MODE (SET_DEST (set)))) > > && push_operand (SET_DEST (set), mode) > > instead? > > push_operand checks the mode by itself: > > --q-- > int > push_operand (rtx op, machine_mode mode) > { > if (!MEM_P (op)) > return 0; > > if (mode != VOIDmode && GET_MODE (op) != mode) > return 0; > ... > -/q- > > Uros. Fixed. Here is the updated patch. OK for master? Thanks. From d44393ab8817002955ba686c1fc08afa53586da7 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 6 Dec 2020 10:43:16 -0800 Subject: [PATCH] x86: Check mode of pseudo register push commit 266f44a91c0c9705d3d18e82d7c5bab32927a18f Author: H.J. Lu Date: Sun May 17 10:10:34 2020 -0700 x86: Allow V1TI vector register pushes Add V1TI vector register push and split it after reload to a sequence of: (set (reg:P SP_REG) (plus:P SP_REG) (const_int -8))) (set (match_dup 0) (match_dup 1)) added a pseudo register push check. But (insn 13 12 14 3 (set (mem:SI (pre_dec:SI (reg/f:SI 7 sp)) [0 S4 A32]) (reg/v:SI 87 [ srclen ])) "x.c":37:16 54 {*pushsi2} (expr_list:REG_DEAD (reg/v:SI 87 [ srclen ]) (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) (nil)))) is not a pseudo register push. In 64-bit mode, mode of pseudo register push is TImode. In 32-bit mode, it is DImode. Add pseudo register push mode check to pseudo_reg_set. gcc/ PR target/98161 * config/i386/i386-features.c (pseudo_reg_set): Check mode of pseudo register push. gcc/testsuite/ * gcc.target/i386/pr98161.c: New test. --- gcc/config/i386/i386-features.c | 3 +- gcc/testsuite/gcc.target/i386/pr98161.c | 48 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr98161.c diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c index ff6676f54f7..c61685bd2f5 100644 --- a/gcc/config/i386/i386-features.c +++ b/gcc/config/i386/i386-features.c @@ -1266,9 +1266,10 @@ pseudo_reg_set (rtx_insn *insn) return NULL; /* Check pseudo register push first. */ + machine_mode mode = TARGET_64BIT ? TImode : DImode; if (REG_P (SET_SRC (set)) && !HARD_REGISTER_P (SET_SRC (set)) - && push_operand (SET_DEST (set), GET_MODE (SET_DEST (set)))) + && push_operand (SET_DEST (set), mode)) return set; df_ref ref; diff --git a/gcc/testsuite/gcc.target/i386/pr98161.c b/gcc/testsuite/gcc.target/i386/pr98161.c new file mode 100644 index 00000000000..5825b9bd1db --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98161.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse4" } */ +/* { dg-require-effective-target sse4} */ + +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned char u8; + +u32 +__attribute__((__force_align_arg_pointer__)) +unreach(const u16 * pu16, u16 *dst, u32 dstlen, const u8 *src, u32 srclen) +{ + for (u32 i = dstlen; srclen && i; i--, srclen--, src++, dst++) + { + u16 off = pu16[*src]; + if (off) + { + src++; srclen--; + *dst = pu16[off + *src]; + } + } + return 56; +} + +u32 +__attribute__((__force_align_arg_pointer__)) +__attribute__((noipa)) +bug(const u16 * pu16, u16 *dst, u32 dstlen, const u8 *src, u32 srclen) +{ + if (pu16) + /* Branch should not execute, but stack realignment + * reads wrong 'pu16' value from stack. */ + return unreach(pu16, dst, dstlen, src, srclen); + + return (srclen < dstlen) ? srclen : dstlen; +} + +int +main() +{ + if (__builtin_cpu_supports ("sse4.1")) + { + /* Should return 12 */ + if (bug(0, 0, 12, 0, 34) != 12) + __builtin_abort (); + } + return 0; +} -- 2.28.0