From patchwork Thu Oct 13 20:07:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 119596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 6635AB71D7 for ; Fri, 14 Oct 2011 07:08:22 +1100 (EST) Received: (qmail 30407 invoked by alias); 13 Oct 2011 20:08:18 -0000 Received: (qmail 30394 invoked by uid 22791); 13 Oct 2011 20:08:16 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-qy0-f182.google.com (HELO mail-qy0-f182.google.com) (209.85.216.182) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 13 Oct 2011 20:07:55 +0000 Received: by qyk4 with SMTP id 4so1603342qyk.20 for ; Thu, 13 Oct 2011 13:07:54 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.87.137 with SMTP id w9mr1100127qcl.284.1318536474216; Thu, 13 Oct 2011 13:07:54 -0700 (PDT) Received: by 10.229.83.146 with HTTP; Thu, 13 Oct 2011 13:07:54 -0700 (PDT) In-Reply-To: <11110131815.AA21002@vlsi1.ultra.nyu.edu> References: <20111012223450.GA11516@intel.com> <11110122240.AA07538@vlsi1.ultra.nyu.edu> <11110122304.AA07835@vlsi1.ultra.nyu.edu> <4E96BAA6.9000809@gnu.org> <11110131251.AA14799@vlsi1.ultra.nyu.edu> <4E96E571.3060006@gnu.org> <11110131414.AA16597@vlsi1.ultra.nyu.edu> <11110131611.AA19261@vlsi1.ultra.nyu.edu> <11110131635.AA19765@vlsi1.ultra.nyu.edu> <4E97197B.8080102@gnu.org> <11110131706.AA20218@vlsi1.ultra.nyu.edu> <11110131815.AA21002@vlsi1.ultra.nyu.edu> Date: Thu, 13 Oct 2011 13:07:54 -0700 Message-ID: Subject: Re: PATCH: PR rtl-optimization/50696: [x32] Unnecessary lea From: "H.J. Lu" To: Richard Kenner Cc: bonzini@gnu.org, gcc-patches@gcc.gnu.org X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Thu, Oct 13, 2011 at 11:15 AM, Richard Kenner wrote: >> The answer to H.J.'s "Why do we do it for MEM then?" is simply >> "because no one ever thought about not doing it" > > No, that's false.  The same expand_compound_operation / make_compound_operation > pair is present in the MEM case as in the SET case.  It's just that > there's some bug here that's noticable in not making proper MEMs that > doesn't show up in the SET case because of the way the insns are structured. > When we have (and (OP) M) where (and (OP) M) == (and (OP) ((1 << ceil_log2 (M)) - 1) )) (and (OP) M) is zero_extract bits 0 to ceil_log2 (M). Does it look OK? Thanks. diff --git a/gcc/combine.c b/gcc/combine.c index 6c3b17c..5962b1d 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -7758,6 +7758,23 @@ make_compound_operation (rtx x, enum rtx_code in_code) next_code), i, NULL_RTX, 1, 1, 0, 1); + + /* If we are (and (OP) M) and M is an extraction mask, this is an + extraction. */ + else + { + unsigned HOST_WIDE_INT nonzero = + nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))); + unsigned HOST_WIDE_INT mask = INTVAL (XEXP (x, 1)); + unsigned HOST_WIDE_INT len = ceil_log2 (mask); + if ((nonzero & (((unsigned HOST_WIDE_INT) 1 << len) - 1)) + == (nonzero & mask)) + { + new_rtx = make_compound_operation (XEXP (x, 0), next_code); + new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, + len, 1, 0, in_code == COMPARE); + } + } break; case LSHIFTRT: