diff mbox series

Enable memory operand for vfpclass[p,s][s,d] patterns.

Message ID CAMZc-byQArC5JN4DNkWMAKHJQELC2sqPzRNcP+0fd7duJ1qU0A@mail.gmail.com
State New
Headers show
Series Enable memory operand for vfpclass[p,s][s,d] patterns. | expand

Commit Message

Hongtao Liu June 5, 2019, 7:39 a.m. UTC 
Hi Jeff and Jakub:
  When adding new intrinsics(PR target/89803), i found vfpclassp[sd],
vfpclasss[sd] patterns didn't support memory operand which is
supported in instructions. So this patch is about to enable memory
operands for vfpclassp[s,d]/vfpclasss[s,d] patterns.

Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
ok for trunk?

Changelog
gcc/
2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>

* config/i386/sse.md (define_mode_suffix vecmemsuffix): New.
(define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"):
Enable memory operand for it.
(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"): Ditto.

gcc/testsuite/
2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>

* gcc.target/i386/avx512dq-vfpclasspd-1.c:
Adjust scan assember for {x,y,z} suffix.
* gcc.target/i386/avx512dq-vfpclassps-1.c: Ditto.

--
BR,
Hongtao

Comments

Jeff Law June 5, 2019, 10:18 p.m. UTC | #1 
On 6/5/19 1:39 AM, Hongtao Liu wrote:
> Hi Jeff and Jakub:
>   When adding new intrinsics(PR target/89803), i found vfpclassp[sd],
> vfpclasss[sd] patterns didn't support memory operand which is
> supported in instructions. So this patch is about to enable memory
> operands for vfpclassp[s,d]/vfpclasss[s,d] patterns.
> 
> Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
> ok for trunk?
> 
> Changelog
> gcc/
> 2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>
> 
> * config/i386/sse.md (define_mode_suffix vecmemsuffix): New.
> (define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"):
> Enable memory operand for it.
> (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"): Ditto.
> 
> gcc/testsuite/
> 2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>
> 
> * gcc.target/i386/avx512dq-vfpclasspd-1.c:
> Adjust scan assember for {x,y,z} suffix.
> * gcc.target/i386/avx512dq-vfpclassps-1.c: Ditto.
OK, but make sure you fix the ChangeLog formatting as you commit.

jeff
Hongtao Liu June 6, 2019, 1:19 a.m. UTC | #2 
On Thu, Jun 6, 2019 at 6:18 AM Jeff Law <law@redhat.com> wrote:
>
> On 6/5/19 1:39 AM, Hongtao Liu wrote:
> > Hi Jeff and Jakub:
> >   When adding new intrinsics(PR target/89803), i found vfpclassp[sd],
> > vfpclasss[sd] patterns didn't support memory operand which is
> > supported in instructions. So this patch is about to enable memory
> > operands for vfpclassp[s,d]/vfpclasss[s,d] patterns.
> >
> > Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
> > ok for trunk?
> >
> > Changelog
> > gcc/
> > 2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>
> >
> > * config/i386/sse.md (define_mode_suffix vecmemsuffix): New.
> > (define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"):
> > Enable memory operand for it.
> > (define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"): Ditto.
> >
> > gcc/testsuite/
> > 2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>
> >
> > * gcc.target/i386/avx512dq-vfpclasspd-1.c:
> > Adjust scan assember for {x,y,z} suffix.
> > * gcc.target/i386/avx512dq-vfpclassps-1.c: Ditto.
> OK, but make sure you fix the ChangeLog formatting as you commit.
>
> jeff

Thanks.

Committed:
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=271984.
diff mbox series

Patch

Index: gcc/config/i386/sse.md
===================================================================
--- gcc/config/i386/sse.md	(revision 271946)
+++ gcc/config/i386/sse.md	(working copy)
@@ -595,6 +595,10 @@ 
 (define_mode_attr ssequarterinsnmode
   [(V16SF "V4SF") (V8DF "V2DF") (V16SI "TI") (V8DI "TI")])
 
+(define_mode_attr vecmemsuffix
+  [(V16SF "{z}") (V8SF "{y}") (V4SF "{x}")
+   (V8DF "{z}") (V4DF "{y}") (V2DF "{x}")])
+
 (define_mode_attr ssedoublemodelower
   [(V16QI "v16hi") (V32QI "v32hi") (V64QI "v64hi")
    (V8HI "v8si")   (V16HI "v16si") (V32HI "v32si")
@@ -21317,11 +21321,11 @@ 
 (define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
           (unspec:<avx512fmaskmode>
-            [(match_operand:VF_AVX512VL 1 "register_operand" "v")
+            [(match_operand:VF_AVX512VL 1 "vector_operand" "vm")
              (match_operand:QI 2 "const_0_to_255_operand" "n")]
              UNSPEC_FPCLASS))]
    "TARGET_AVX512DQ"
-   "vfpclass<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
+   "vfpclass<ssemodesuffix><vecmemsuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
   [(set_attr "type" "sse")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "evex")
@@ -21331,7 +21335,7 @@ 
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
 	(and:<avx512fmaskmode>
 	  (unspec:<avx512fmaskmode>
-	    [(match_operand:VF_128 1 "register_operand" "v")
+	    [(match_operand:VF_128 1 "vector_operand" "vm")
              (match_operand:QI 2 "const_0_to_255_operand" "n")]
 	    UNSPEC_FPCLASS)
 	  (const_int 1)))]
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclasspd-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclasspd-1.c	(revision 271946)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclasspd-1.c	(working copy)
@@ -1,11 +1,11 @@ 
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -mavx512vl -O2" } */
-/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspdz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspdy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspdx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspdz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspdy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspdx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>
 
Index: gcc/testsuite/gcc.target/i386/avx512dq-vfpclassps-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx512dq-vfpclassps-1.c	(revision 271946)
+++ gcc/testsuite/gcc.target/i386/avx512dq-vfpclassps-1.c	(working copy)
@@ -1,11 +1,11 @@ 
 /* { dg-do compile } */
 /* { dg-options "-mavx512dq -mavx512vl -O2" } */
-/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspsz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspsy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspsx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspsz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspsy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfpclasspsx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
 
 #include <immintrin.h>