From patchwork Tue Dec 1 05:17:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongtao Liu X-Patchwork-Id: 1408623 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=bo3bzreR; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4ClVgX5R2tz9sVk for ; Tue, 1 Dec 2020 16:16:06 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1F2363861810; Tue, 1 Dec 2020 05:16:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1F2363861810 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1606799763; bh=+u1R79kdM7f2ASdoFqxwcTpeo2PcF6dEwJ+C6Ig7j84=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=bo3bzreRasZrU716T+6dFziwzAfaeYToTX1zlSDbqpng54+LI6cpOzs/SfJec5wl2 mG8GNs/SRy5kIjYrHm/OrYkWDP31LKz+oKBdrrSCT3wjJwfZlpl9ZpyAxouChLLQbC FqVP21P127PSPDTZcfEoYnqDkK7giYugLFK7mzpY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-vk1-xa2c.google.com (mail-vk1-xa2c.google.com [IPv6:2607:f8b0:4864:20::a2c]) by sourceware.org (Postfix) with ESMTPS id 19E973851C21 for ; Tue, 1 Dec 2020 05:15:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 19E973851C21 Received: by mail-vk1-xa2c.google.com with SMTP id a4so150239vko.11 for ; Mon, 30 Nov 2020 21:15:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=+u1R79kdM7f2ASdoFqxwcTpeo2PcF6dEwJ+C6Ig7j84=; b=t5AGuuTHzWCYBxaZ1tZJaiH/Rc+9srAZr25UqHvpX/UW+u3JtVK5w/Bdn55QPpJOts 8WJ77nbijPugTcQ3mcCI9C38QuW1KjEnxzfM6kKZozU3d6i5WxqpGRgyxJn8RdgY9arJ jgN0W1KgMpq3Y3ZGy+lO8SBwU7ovpWYFw6vLxiNyy1ASfwdSErtc557Kf/yip0Zd2mqC eNMwqq0pzNMmt/guCodwMzjuaQD8H07ol9TkyDdKwUMSHHr6H1lzcXpzNNa+KEbwXYTw OIRjcxMMMmzdRFlRcqL/f0NlYdq93XrZ1O8CibEEudbaFKh4m5D8o0HhyLEdVH5ey7+1 hXAQ== X-Gm-Message-State: AOAM533DCkJxp71E8TyOmiFfTw5De1SKeLgIIfzHYW8ypPusZorb2Wl1 nM9MQ14V0xVAinuIwGaQRq7zJP/Ju1bOc15miniJnAjg0yAAWE9M X-Google-Smtp-Source: ABdhPJyA6gF12zaaxrxmh+1ZTNqM3+ISMA4zkOb+ZTHDCY8LiqPJpsMUFJRaZFbbitGBKFWzDAGzsvd3HL44SsSsrfY= X-Received: by 2002:a1f:2c01:: with SMTP id s1mr1086985vks.11.1606799758377; Mon, 30 Nov 2020 21:15:58 -0800 (PST) MIME-Version: 1.0 Date: Tue, 1 Dec 2020 13:17:38 +0800 Message-ID: Subject: [PATCH] [Refactor] [AVX512] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW To: GCC Patches X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hongtao Liu via Gcc-patches From: Hongtao Liu Reply-To: Hongtao Liu Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi: There're many pairs of define_insn/define_expand that are very similar to each other except mode iterator and condition. For these patterns VI12_AVX512VL are used under condition TARGET_AVX512BW, and VI48_AVX512VL are used under condition TARGET_AVX512F. This patch is about to introduce a new iterator VI_AVX512VLBW to combine a pair of those patterns into one. There are no functional changes, just code refactoring. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? gcc/ChangeLog * config/i386/sse.md (VI_AVX512VLBW): New mode iterator. (_ucmp3): Combine two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL into one pattern with mode iterator VI_AVX512VLBW. (vec_cmpu): Ditto. (_cvt2mask): Ditto. (_cvtmask2): Ditto. (*_cvtmask2): Ditto. (3_mask): Ditto. (*3_mask): Ditto. (_eq3): Ditto. (_eq3_1): Ditto. (_gt3): Ditto. (_andnot3_mask): Ditto. (abs2_mask): Ditto. (*_3): Combine from ... (*avx512f_3) and (3). From e55528fb9a0346365327e7b1cdebadec7c71be15 Mon Sep 17 00:00:00 2001 From: liuhongt Date: Mon, 30 Nov 2020 13:24:45 +0800 Subject: [PATCH] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW. There're many pairs of define_insn/define_expand that are very similar to each other except mode iterator and condition. For these patterns VI12_AVX512VL are used under condition TARGET_AVX512BW, and VI48_AVX512VL are used under condition TARGET_AVX512F. This patch is about to introduce a new iterator VI_AVX512VLBW to combine a pair of those patterns into one. There're no functional changed, just code refactoring. gcc/ChangeLog * config/i386/sse.md (VI_AVX512VLBW): New mode iterator. (_ucmp3): Combine two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL into one pattern with mode iterator VI_AVX512VLBW. (vec_cmpu): Ditto. (_cvt2mask): Ditto. (_cvtmask2): Ditto. (*_cvtmask2): Ditto. (3_mask): Ditto. (*3_mask): Ditto. (_eq3): Ditto. (_eq3_1): Ditto. (_gt3): Ditto. (_andnot3_mask): Ditto. (abs2_mask): Ditto. (*_3): Combine from ... (*avx512f_3) and (3). --- gcc/config/i386/sse.md | 312 ++++++++++++----------------------------- 1 file changed, 89 insertions(+), 223 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4aad462f882..c761a018e86 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -335,6 +335,14 @@ (define_mode_iterator VI48_AVX512VL [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) +(define_mode_iterator VI_AVX512VLBW + [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + (V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") + (V16QI "TARGET_AVX512BW && TARGET_AVX512VL") + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW") + (V8HI "TARGET_AVX512VL && TARGET_AVX512BW")]) + (define_mode_iterator VF_AVX512VL [V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) @@ -2981,25 +2989,11 @@ (define_insn "_cmp3" (define_insn "_ucmp3" [(set (match_operand: 0 "register_operand" "=k") (unspec: - [(match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm") + [(match_operand:VI_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm") (match_operand:SI 3 "const_0_to_7_operand" "n")] UNSPEC_UNSIGNED_PCMP))] - "TARGET_AVX512BW" - "vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "type" "ssecmp") - (set_attr "length_immediate" "1") - (set_attr "prefix" "evex") - (set_attr "mode" "")]) - -(define_insn "_ucmp3" - [(set (match_operand: 0 "register_operand" "=k") - (unspec: - [(match_operand:VI48_AVX512VL 1 "register_operand" "v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_7_operand" "n")] - UNSPEC_UNSIGNED_PCMP))] - "TARGET_AVX512F" + "" "vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") @@ -3149,22 +3143,9 @@ (define_expand "vec_cmp" (define_expand "vec_cmpu" [(set (match_operand: 0 "register_operand") (match_operator: 1 "" - [(match_operand:VI48_AVX512VL 2 "register_operand") - (match_operand:VI48_AVX512VL 3 "nonimmediate_operand")]))] - "TARGET_AVX512F" -{ - bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]), - operands[2], operands[3]); - gcc_assert (ok); - DONE; -}) - -(define_expand "vec_cmpu" - [(set (match_operand: 0 "register_operand") - (match_operator: 1 "" - [(match_operand:VI12_AVX512VL 2 "register_operand") - (match_operand:VI12_AVX512VL 3 "nonimmediate_operand")]))] - "TARGET_AVX512BW" + [(match_operand:VI_AVX512VLBW 2 "register_operand") + (match_operand:VI_AVX512VLBW 3 "nonimmediate_operand")]))] + "" { bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]), operands[2], operands[3]); @@ -6428,71 +6409,53 @@ (define_insn "vec_unpacks_lo_v16sf" (define_insn "_cvt2mask" [(set (match_operand: 0 "register_operand" "=k") (unspec: - [(match_operand:VI12_AVX512VL 1 "register_operand" "v")] - UNSPEC_CVTINT2MASK))] - "TARGET_AVX512BW" - "vpmov2m\t{%1, %0|%0, %1}" - [(set_attr "prefix" "evex") - (set_attr "mode" "")]) - -(define_insn "_cvt2mask" - [(set (match_operand: 0 "register_operand" "=k") - (unspec: - [(match_operand:VI48_AVX512VL 1 "register_operand" "v")] + [(match_operand:VI_AVX512VLBW 1 "register_operand" "v")] UNSPEC_CVTINT2MASK))] - "TARGET_AVX512DQ" + "TARGET_AVX512DQ || GET_MODE_SIZE (GET_MODE_INNER (mode)) < 4" "vpmov2m\t{%1, %0|%0, %1}" [(set_attr "prefix" "evex") (set_attr "mode" "")]) (define_expand "_cvtmask2" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW (match_dup 2) (match_dup 3) (match_operand: 1 "register_operand")))] - "TARGET_AVX512BW" - { - operands[2] = CONSTM1_RTX (mode); - operands[3] = CONST0_RTX (mode); - }) - -(define_insn "*_cvtmask2" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (match_operand:VI12_AVX512VL 2 "vector_all_ones_operand") - (match_operand:VI12_AVX512VL 3 "const0_operand") - (match_operand: 1 "register_operand" "k")))] - "TARGET_AVX512BW" - "vpmovm2\t{%1, %0|%0, %1}" - [(set_attr "prefix" "evex") - (set_attr "mode" "")]) - -(define_expand "_cvtmask2" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (match_dup 2) - (match_dup 3) - (match_operand: 1 "register_operand")))] - "TARGET_AVX512F" + "" "{ operands[2] = CONSTM1_RTX (mode); operands[3] = CONST0_RTX (mode); }") (define_insn "*_cvtmask2" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v,v") - (vec_merge:VI48_AVX512VL - (match_operand:VI48_AVX512VL 2 "vector_all_ones_operand") - (match_operand:VI48_AVX512VL 3 "const0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v,v") + (vec_merge:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 2 "vector_all_ones_operand") + (match_operand:VI_AVX512VLBW 3 "const0_operand") (match_operand: 1 "register_operand" "k,Yk")))] - "TARGET_AVX512F" + "" "@ vpmovm2\t{%1, %0|%0, %1} vpternlog\t{$0x81, %0, %0, %0%{%1%}%{z%}|%0%{%1%}%{z%}, %0, %0, 0x81}" - [(set_attr "isa" "avx512dq,*") + [(set (attr "isa") + (cond [(eq_attr "alternative" "0") + (if_then_else + (match_test "GET_MODE_SIZE (GET_MODE_INNER (mode)) > 2") + (const_string "avx512dq") + (const_string "*")) + ] + (const_string "*"))) (set_attr "length_immediate" "0,1") (set_attr "prefix" "evex") + (set (attr "enabled") + (cond [(eq_attr "alternative" "1") + (if_then_else + (match_test "GET_MODE_SIZE (GET_MODE_INNER (mode)) < 4") + (symbol_ref "false") + (const_string "*")) + ] + (const_string "*"))) (set_attr "mode" "")]) (define_insn "sse2_cvtps2pd" @@ -11334,25 +11297,14 @@ (define_expand "3" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_expand "3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (plusminus:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW + (plusminus:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand") (match_operand: 4 "register_operand")))] - "TARGET_AVX512F" - "ix86_fixup_binary_operands_no_copy (, mode, operands);") - -(define_expand "3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL - (plusminus:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand") - (match_operand: 4 "register_operand")))] - "TARGET_AVX512BW" + "" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_insn "*3" @@ -11371,28 +11323,14 @@ (define_insn "*3" (set_attr "mode" "")]) (define_insn "*3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI48_AVX512VL - (plusminus:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand" "0C") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v") + (vec_merge:VI_AVX512VLBW + (plusminus:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand" "v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand" "0C") (match_operand: 4 "register_operand" "Yk")))] - "TARGET_AVX512F && ix86_binary_operator_ok (, mode, operands)" - "vp\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix" "evex") - (set_attr "mode" "")]) - -(define_insn "*3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (plusminus:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand" "0C") - (match_operand: 4 "register_operand" "Yk")))] - "TARGET_AVX512BW && ix86_binary_operator_ok (, mode, operands)" + "ix86_binary_operator_ok (, mode, operands)" "vp\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix" "evex") @@ -12309,37 +12247,25 @@ (define_insn "*avx2_3" (set_attr "mode" "OI")]) (define_expand "3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (maxmin:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW + (maxmin:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand") (match_operand: 4 "register_operand")))] - "TARGET_AVX512F" + "" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*avx512f_3" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") - (maxmin:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "vp\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_evex") - (set_attr "mode" "")]) - -(define_insn "3" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (maxmin:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512BW" +(define_insn "*_3" + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v") + (maxmin:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand" "%v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm")))] + "!(MEM_P (operands[1]) && MEM_P (operands[2]))" "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") - (set_attr "prefix" "evex") + (set_attr "prefix" "") (set_attr "mode" "")]) (define_expand "3" @@ -12572,41 +12498,17 @@ (define_insn "*avx2_eq3" (define_expand "_eq3" [(set (match_operand: 0 "register_operand") (unspec: - [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")] + [(match_operand:VI_AVX512VLBW 1 "nonimmediate_operand") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")] UNSPEC_MASKED_EQ))] - "TARGET_AVX512BW" - "ix86_fixup_binary_operands_no_copy (EQ, mode, operands);") - -(define_expand "_eq3" - [(set (match_operand: 0 "register_operand") - (unspec: - [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")] - UNSPEC_MASKED_EQ))] - "TARGET_AVX512F" + "" "ix86_fixup_binary_operands_no_copy (EQ, mode, operands);") (define_insn "_eq3_1" [(set (match_operand: 0 "register_operand" "=k,k") (unspec: - [(match_operand:VI12_AVX512VL 1 "nonimm_or_0_operand" "%v,v") - (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "vm,C")] - UNSPEC_MASKED_EQ))] - "TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "@ - vpcmpeq\t{%2, %1, %0|%0, %1, %2} - vptestnm\t{%1, %1, %0|%0, %1, %1}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "evex") - (set_attr "mode" "")]) - -(define_insn "_eq3_1" - [(set (match_operand: 0 "register_operand" "=k,k") - (unspec: - [(match_operand:VI48_AVX512VL 1 "nonimm_or_0_operand" "%v,v") - (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "vm,C")] + [(match_operand:VI_AVX512VLBW 1 "nonimm_or_0_operand" "%v,v") + (match_operand:VI_AVX512VLBW 2 "nonimm_or_0_operand" "vm,C")] UNSPEC_MASKED_EQ))] "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ @@ -12696,21 +12598,9 @@ (define_insn "avx2_gt3" (define_insn "_gt3" [(set (match_operand: 0 "register_operand" "=k") (unspec: - [(match_operand:VI48_AVX512VL 1 "register_operand" "v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))] - "TARGET_AVX512F" - "vpcmpgt\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "evex") - (set_attr "mode" "")]) - -(define_insn "_gt3" - [(set (match_operand: 0 "register_operand" "=k") - (unspec: - [(match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))] - "TARGET_AVX512BW" + [(match_operand:VI_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))] + "" "vpcmpgt\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecmp") (set_attr "prefix_extra" "1") @@ -12950,26 +12840,15 @@ (define_expand "_andnot3" "TARGET_SSE2") (define_expand "_andnot3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (and:VI48_AVX512VL - (not:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "register_operand")) - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") - (match_operand: 4 "register_operand")))] - "TARGET_AVX512F") - -(define_expand "_andnot3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL - (and:VI12_AVX512VL - (not:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand")) - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW + (and:VI_AVX512VLBW + (not:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "register_operand")) + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand") (match_operand: 4 "register_operand")))] - "TARGET_AVX512BW") + "") (define_insn "*andnot3" [(set (match_operand:VI 0 "register_operand" "=x,x,v") @@ -16874,11 +16753,11 @@ (define_insn "*abs2" (set_attr "mode" "")]) (define_insn "abs2_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI48_AVX512VL - (abs:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm")) - (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "0C") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v") + (vec_merge:VI_AVX512VLBW + (abs:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand" "vm")) + (match_operand:VI_AVX512VLBW 2 "nonimm_or_0_operand" "0C") (match_operand: 3 "register_operand" "Yk")))] "TARGET_AVX512F" "vpabs\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" @@ -16886,19 +16765,6 @@ (define_insn "abs2_mask" (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "abs2_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (abs:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm")) - (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C") - (match_operand: 3 "register_operand" "Yk")))] - "TARGET_AVX512BW" - "vpabs\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" - [(set_attr "type" "sselog1") - (set_attr "prefix" "evex") - (set_attr "mode" "")]) - (define_expand "abs2" [(set (match_operand:VI_AVX2 0 "register_operand") (abs:VI_AVX2 -- 2.18.1