From patchwork Tue Oct 16 02:50:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 984494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-487607-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="lG16LOPh"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FcZ9PbII"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Z0D83CrJz9s9J for ; Tue, 16 Oct 2018 13:50:32 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=mnhjKslf1gJJTfohXyWzsgRIoP2BzX9uvboJYKRr/yy gDiH8TFW1IjBMVvM3y7dCeWytXOcj5kzYBUXHJu9rW5IUId/yKJVa5rr0hOgz8jq 0wP9/GomK6mVSlqmInVxxQ2ZLgFceHjHLtOeRxccgL7im/x/8LVh2mBeFAnX2hTM = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=dS+bWyihjEKCsbUw4T9oUWSfDZ4=; b=lG16LOPhxUGPLMoBe ijZ8ViDl7izHioYE7HvJa+yXPTtairReY3m0JiB7TYQss4Qsvit4BeO22XpEDzR3 hcRbbdvyZTy7KpjplS4Y9kQgklu3ebJCwQPtYnxb0mPOi+QhRsE1dSzeL22Q0NWO H640rqji/FSYgztkzVHuYOE3KU= Received: (qmail 90496 invoked by alias); 16 Oct 2018 02:50:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90464 invoked by uid 89); 16 Oct 2018 02:50:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-ot1-f46.google.com Received: from mail-ot1-f46.google.com (HELO mail-ot1-f46.google.com) (209.85.210.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Oct 2018 02:50:22 +0000 Received: by mail-ot1-f46.google.com with SMTP id o21so20986636otb.13 for ; Mon, 15 Oct 2018 19:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=izxxezyf0qjsKvwy2WMOt0nJsu53XHRBcwYqtDT0Z4A=; b=FcZ9PbIItAfG34D3FGJev5TExiUt69dMRh7aX46iUy7XP2VSSsRjz4vj9p8KaXd+ZB 9vFGjtE5U+k0rOCLX33V/KaG/2U4rDiHf3HyelziVPXXn1ftkbbJTWcyEciL7jFPHUUl wkhPxaUSNtpu3Tn6UPOA5nmWCzRljmiiLNBTU57QjbqeyMXqkL07g0Wef7Zwl/bk0TBq JwMhwOQgSyFuEkf5LL6PZbwiUkVHClK47sKcCopfVHBbIMPSfPeOXVGuE0yOOcQPrIlR aLBbmNDvbwaHVsIOkU1wr9mrKuIoPM9CchukLy6m5w/Q87mBPAYXs1N7hb/WWPrQnQ+P ajZw== MIME-Version: 1.0 From: Paul Hua Date: Tue, 16 Oct 2018 10:50:08 +0800 Message-ID: Subject: [PATCH v3 2/6] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a To: gcc-patches Cc: Matthew Fortune , "Jeff Law (law@redhat.com)" X-IsSubscribed: yes From 2e053c832497892c6b8b1b685aaf871d8fc4da76 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 11:52:33 +0800 Subject: [PATCH 2/6] Add support for Loongson EXT istructions. gcc/ * config/mips/mips.c (mips_option_override): Default enable Loongson EXT on Loongson 3a target. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_ext. (ASM_SPEC): Add mloongson-ext and mno-loongson-ext. * config/mips/mips.md (mul3, mul3_mul3_nohilo, div3, mod3, prefetch): Use TARGET_LOONGSON_EXT instead of TARGET_LOONGSON_3A. * config/mips/mips.opt (-mloongson-ext): Add option. * gcc/doc/invoke.texi (-mloongson-ext): Document. gcc/testsuite/ * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext option. --- gcc/config/mips/mips.c | 5 +++++ gcc/config/mips/mips.h | 7 +++++++ gcc/config/mips/mips.md | 16 ++++++++-------- gcc/config/mips/mips.opt | 4 ++++ gcc/doc/invoke.texi | 7 +++++++ gcc/testsuite/gcc.target/mips/mips.exp | 1 + 6 files changed, 32 insertions(+), 8 deletions(-) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index a804f7030db..019a6dca752 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -20178,6 +20178,11 @@ mips_option_override (void) || (strcmp (mips_arch_info->name, "loongson3a") == 0))) target_flags |= MASK_LOONGSON_MMI; + /* Default to enable Loongson EXT on Longson 3a target. */ + if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 + && (strcmp (mips_arch_info->name, "loongson3a") == 0)) + target_flags |= MASK_LOONGSON_EXT; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 3563c1d78fe..e0e78ba610e 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -596,6 +596,12 @@ struct mips_cpu_info { builtin_define ("__mips_loongson_mmi"); \ } \ \ + /* Whether Loongson EXT modes are enabled. */ \ + if (TARGET_LOONGSON_EXT) \ + { \ + builtin_define ("__mips_loongson_ext"); \ + } \ + \ /* Historical Octeon macro. */ \ if (TARGET_OCTEON) \ builtin_define ("__OCTEON__"); \ @@ -1355,6 +1361,7 @@ struct mips_cpu_info { %{mginv} %{mno-ginv} \ %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ +%{mloongson-ext} %{mno-loongson-ext} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index a88c1c53134..4b7a627b7a6 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1599,7 +1599,7 @@ { rtx lo; - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL) emit_insn (gen_mul3_mul3_nohilo (operands[0], operands[1], operands[2])); else if (ISA_HAS_MUL3) @@ -1622,11 +1622,11 @@ [(set (match_operand:GPR 0 "register_operand" "=d") (mult:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL" { if (TARGET_LOONGSON_2EF) return "multu.g\t%0,%1,%2"; - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return "gsmultu\t%0,%1,%2"; else return "mul\t%0,%1,%2"; @@ -3016,11 +3016,11 @@ [(set (match_operand:GPR 0 "register_operand" "=&d") (any_div:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV" { if (TARGET_LOONGSON_2EF) return mips_output_division ("div.g\t%0,%1,%2", operands); - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return mips_output_division ("gsdiv\t%0,%1,%2", operands); else return mips_output_division ("div\t%0,%1,%2", operands); @@ -3032,11 +3032,11 @@ [(set (match_operand:GPR 0 "register_operand" "=&d") (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV" { if (TARGET_LOONGSON_2EF) return mips_output_division ("mod.g\t%0,%1,%2", operands); - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return mips_output_division ("gsmod\t%0,%1,%2", operands); else return mips_output_division ("mod\t%0,%1,%2", operands); @@ -7136,7 +7136,7 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) { /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ if (TARGET_64BIT) diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 6767c47fa65..a8fe8db3c66 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -463,3 +463,7 @@ Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS) mloongson-mmi Target Report Mask(LOONGSON_MMI) Use Loongson MultiMedia extensions Instructions (MMI) instructions. + +mloongson-ext +Target Report Mask(LOONGSON_EXT) +Use Loongson EXTension (EXT) instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 79544e2c2b6..5f2736b9e09 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -920,6 +920,7 @@ Objective-C and Objective-C++ Dialects}. -mmicromips -mno-micromips @gol -mmsa -mno-msa @gol -mloongson-mmi -mno-loongson-mmi @gol +-mloongson-ext -mno-loongson-ext @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -21263,6 +21264,12 @@ Use (do not use) the MIPS Global INValidate (GINV) instructions. @opindex mno-loongson-mmi Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). +@item -mloongson-ext +@itemx -mno-loongson-ext +@opindex mloongson-ext +@opindex mno-loongson-ext +Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 4045c593a6c..70f7a996f8d 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -297,6 +297,7 @@ foreach option { odd-spreg msa loongson-mmi + loongson-ext } { lappend mips_option_groups $option "-m(no-|)$option" } -- 2.11.0