From patchwork Tue Jan 20 22:23:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 431273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D9944140277 for ; Wed, 21 Jan 2015 09:23:18 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=FvVdsmOKNwWNSAw2KY H0hWkjMsb/JGjLqVnGFtajVLhOEdEctj27Z8Rsm19a6t3lLk6A8W1tD/Z8IZytbs 1dtWbBWsM3zUVrfgBg1QBDMTSrYoHh9RywOG4f8pZNSaQ4SQyCJ7i+BWnNSQFa6F uODeMKxhyfkbIdkRjagR1+pho= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=o1iMjjHQhmen8NVuP48hdLOW 1sM=; b=ikzOeMmMLHTF7eeJu+3VNYdgmg35fzejzWrhCYLhvYXj1jA4iY2WZkkI YV99CIj7hIQ0bRTdlRjOS+Ac5JBSTb6FZ5h5FxxjztazxA+K730QIGRskfVakDip Une5kQUuoxMV97HijzdUkEjAIJDlyQTpuO04HaM5k88UelQ/qWo= Received: (qmail 25261 invoked by alias); 20 Jan 2015 22:23:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25251 invoked by uid 89); 20 Jan 2015 22:23:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qc0-f169.google.com Received: from mail-qc0-f169.google.com (HELO mail-qc0-f169.google.com) (209.85.216.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 20 Jan 2015 22:23:08 +0000 Received: by mail-qc0-f169.google.com with SMTP id b13so14754758qcw.0 for ; Tue, 20 Jan 2015 14:23:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=EOVNLVW2Jh2HMzhHvb87wtElgqJvo+QbsXb3xJC3EFI=; b=JwQMvznTe3FhpemBcRh6VXCQ9NM66l2yDn63fhhztBIf2GW57f7cy8Gb1RgQlrNKLc pygxxrPKRN1cYPpXRcpx9BQ9QBdvPCBYgVsGTguakxH23kt201049BThmL6NnINkWLNe /9/KChDSSQLUVBQK6n9fnxIyUUrc3ZPDuKPj0DzN67gR6CFKCYRWp6qYrg1cNn8WnGNa xGgmgVvtBs1okI8RnuAoJo27u7+rmk6+iUKoALELmiGy8cdlaIXG/s/sNbfUGDuxDwiW 4xxSnf6sQzK01t9zdzUPEwEfiEuNVLA3hQxU70W4uhkq6lrMCzYa8celibQsfCgvzbm8 CCrg== X-Gm-Message-State: ALoCoQmJqGBYDOMRIiad7FYzTDQXE9YSQ2j2hQD7KOUybB+kZ+yx4iB+e3uIyDjS0UtehVZhLsrm MIME-Version: 1.0 X-Received: by 10.140.44.134 with SMTP id g6mr47323172qga.85.1421792585306; Tue, 20 Jan 2015 14:23:05 -0800 (PST) Received: by 10.140.84.176 with HTTP; Tue, 20 Jan 2015 14:23:04 -0800 (PST) In-Reply-To: References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> <1421162314-25779-8-git-send-email-christophe.lyon@linaro.org> Date: Tue, 20 Jan 2015 23:23:04 +0100 Message-ID: Subject: Re: [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests. From: Christophe Lyon To: Marcus Shawcroft Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes On 19 January 2015 at 14:39, Marcus Shawcroft wrote: > On 13 January 2015 at 15:18, Christophe Lyon wrote: >> >> * gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file. >> * gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file. >> * gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file. > > OK with Tejas' comment addressed. /Marcus Here is what I have committed (removed poly, int8 and int64 variants). Christophe. Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc =================================================================== --- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc (revision 0) +++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc (working copy) @@ -0,0 +1,100 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ +#define DECL_VMLX_LANE(VAR) \ + DECL_VARIABLE(VAR, int, 16, 4); \ + DECL_VARIABLE(VAR, int, 32, 2); \ + DECL_VARIABLE(VAR, uint, 16, 4); \ + DECL_VARIABLE(VAR, uint, 32, 2); \ + DECL_VARIABLE(VAR, float, 32, 2); \ + DECL_VARIABLE(VAR, int, 16, 8); \ + DECL_VARIABLE(VAR, int, 32, 4); \ + DECL_VARIABLE(VAR, uint, 16, 8); \ + DECL_VARIABLE(VAR, uint, 32, 4); \ + DECL_VARIABLE(VAR, float, 32, 4) + + /* vector_res = vmlx_lane(vector, vector2, vector3, lane), + then store the result. */ +#define TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, L) \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector2, T1, W, N), \ + VECT_VAR(vector3, T1, W, N2), \ + L); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)) + +#define TEST_VMLX_LANE(INSN, Q, T1, T2, W, N, N2, V) \ + TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, V) + + DECL_VMLX_LANE(vector); + DECL_VMLX_LANE(vector2); + DECL_VMLX_LANE(vector_res); + + DECL_VARIABLE(vector3, int, 16, 4); + DECL_VARIABLE(vector3, int, 32, 2); + DECL_VARIABLE(vector3, uint, 16, 4); + DECL_VARIABLE(vector3, uint, 32, 2); + DECL_VARIABLE(vector3, float, 32, 2); + + clean_results (); + + VLOAD(vector, buffer, , int, s, 16, 4); + VLOAD(vector, buffer, , int, s, 32, 2); + VLOAD(vector, buffer, , uint, u, 16, 4); + VLOAD(vector, buffer, , uint, u, 32, 2); + VLOAD(vector, buffer, q, int, s, 16, 8); + VLOAD(vector, buffer, q, int, s, 32, 4); + VLOAD(vector, buffer, q, uint, u, 16, 8); + VLOAD(vector, buffer, q, uint, u, 32, 4); + VLOAD(vector, buffer, , float, f, 32, 2); + VLOAD(vector, buffer, q, float, f, 32, 4); + + VDUP(vector2, , int, s, 16, 4, 0x55); + VDUP(vector2, , int, s, 32, 2, 0x55); + VDUP(vector2, , uint, u, 16, 4, 0x55); + VDUP(vector2, , uint, u, 32, 2, 0x55); + VDUP(vector2, , float, f, 32, 2, 55.3f); + VDUP(vector2, q, int, s, 16, 8, 0x55); + VDUP(vector2, q, int, s, 32, 4, 0x55); + VDUP(vector2, q, uint, u, 16, 8, 0x55); + VDUP(vector2, q, uint, u, 32, 4, 0x55); + VDUP(vector2, q, float, f, 32, 4, 55.8f); + + VDUP(vector3, , int, s, 16, 4, 0xBB); + VDUP(vector3, , int, s, 32, 2, 0xBB); + VDUP(vector3, , uint, u, 16, 4, 0xBB); + VDUP(vector3, , uint, u, 32, 2, 0xBB); + VDUP(vector3, , float, f, 32, 2, 11.34f); + + /* Choose lane arbitrarily. */ + TEST_VMLX_LANE(INSN_NAME, , int, s, 16, 4, 4, 2); + TEST_VMLX_LANE(INSN_NAME, , int, s, 32, 2, 2, 1); + TEST_VMLX_LANE(INSN_NAME, , uint, u, 16, 4, 4, 2); + TEST_VMLX_LANE(INSN_NAME, , uint, u, 32, 2, 2, 1); + TEST_VMLX_LANE(INSN_NAME, , float, f, 32, 2, 2, 1); + TEST_VMLX_LANE(INSN_NAME, q, int, s, 16, 8, 4, 3); + TEST_VMLX_LANE(INSN_NAME, q, int, s, 32, 4, 2, 1); + TEST_VMLX_LANE(INSN_NAME, q, uint, u, 16, 8, 4, 2); + TEST_VMLX_LANE(INSN_NAME, q, uint, u, 32, 4, 2, 1); + TEST_VMLX_LANE(INSN_NAME, q, float, f, 32, 4, 2, 1); + + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c (revision 0) +++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c (working copy) @@ -0,0 +1,23 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmla +#define TEST_MSG "VMLA_LANE" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x3e07, 0x3e08 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3e07, 0x3e08 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4418c687, 0x44190687 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a, + 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a, + 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x441a3168, 0x441a7168, + 0x441ab168, 0x441af168 }; + +#include "vmlX_lane.inc" Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c (revision 0) +++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c (working copy) @@ -0,0 +1,25 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmls +#define TEST_MSG "VMLS_LANE" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffc1d9, 0xffffc1da }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffc1d9, 0xffffc1da }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc420c687, 0xc4208687 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc, + 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da, + 0xffffc1db, 0xffffc1dc }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc, + 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da, + 0xffffc1db, 0xffffc1dc }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4223168, 0xc421f168, + 0xc421b168, 0xc4217168 }; + +#include "vmlX_lane.inc"