| Message ID | CAKdteOY-tjAfjD-sVEqU4ZJWoH=f_nQThHmLzmnOBoFVgYAGVQ@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm: Fix regression in contant handling for -mpure-code for v8m | expand |
Hi, You can disregard this patch, Wilco found problems with it, and I think he is working on a more complete fix. Thanks, Christophe On Thu, 16 Apr 2020 at 17:39, Christophe Lyon <christophe.lyon@linaro.org> wrote: > > Hi, > > In PR94538, Wilco mentioned that my patch to enable -mpure-code for > v6m caused regressions in the code generated for cortex-m23. > > Specifically, for > int f3 (void) { return 0x11000000; } > int f3_bis (void) { return 0x12345678; } > > we currently generate (-O2 -mcpu=cortex-m23 -mpure-code) > movs r0, #17 > lsls r0, r0, #8 > lsls r0, r0, #8 > lsls r0, r0, #8 > bx lr > and > movs r0, #86 > lsls r0, r0, #8 > adds r0, r0, #120 > movt r0, 4660 > bx lr > > The attached patch brings back the original code generation: > movs r0, #136 @ 12 [c=4 l=2] *thumb1_movsi_insn/1 > lsls r0, r0, #21 @ 9 [c=4 l=2] *thumb1_ashlsi3/0 > bx lr > and > movw r0, #22136 @ 12 [c=4 l=4] *thumb1_movsi_insn/2 > movt r0, 4660 @ 13 [c=4 l=4] *arm_movtas_ze/1 > bx lr > > This does not address the other problems discussed in the PR, so I'm > not mentioning it in the ChangeLog. > > OK? > > Thanks, > > Christophe
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 2486163..e2644a9 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -66,11 +66,11 @@ (define_insn "thumb1_movsi_symbol_ref" (define_split [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "immediate_operand" ""))] + (match_operand:SI 1 "const_int_operand" ""))] "TARGET_THUMB1 + && !TARGET_HAVE_MOVT && arm_disable_literal_pool - && GET_CODE (operands[1]) == CONST_INT - && !satisfies_constraint_I (operands[1])" + && !satisfies_constraint_K (operands[1])" [(clobber (const_int 0))] " thumb1_gen_const_int (operands[0], INTVAL (operands[1]));
Hi, In PR94538, Wilco mentioned that my patch to enable -mpure-code for v6m caused regressions in the code generated for cortex-m23. Specifically, for int f3 (void) { return 0x11000000; } int f3_bis (void) { return 0x12345678; } we currently generate (-O2 -mcpu=cortex-m23 -mpure-code) movs r0, #17 lsls r0, r0, #8 lsls r0, r0, #8 lsls r0, r0, #8 bx lr and movs r0, #86 lsls r0, r0, #8 adds r0, r0, #120 movt r0, 4660 bx lr The attached patch brings back the original code generation: movs r0, #136 @ 12 [c=4 l=2] *thumb1_movsi_insn/1 lsls r0, r0, #21 @ 9 [c=4 l=2] *thumb1_ashlsi3/0 bx lr and movw r0, #22136 @ 12 [c=4 l=4] *thumb1_movsi_insn/2 movt r0, 4660 @ 13 [c=4 l=4] *arm_movtas_ze/1 bx lr This does not address the other problems discussed in the PR, so I'm not mentioning it in the ChangeLog. OK? Thanks, Christophe gcc/ChangeLog: 2020-04-16 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/thumb1.md: Fix mov splitter for arm_disable_literal_pool.