From patchwork Mon Jun 15 22:15:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Edelsohn X-Patchwork-Id: 484611 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 36C01140284 for ; Tue, 16 Jun 2015 08:15:56 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=pDbn3iOf; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=F38aeFs9uL2RgB0OOIvUMJjt+sW/DRfB8FHqq2uMNrQ0Eo wC9LcNSlsY7yu/LCoi0c8HLnQu6F9YfKzFx8g9cZsuM1ZBQhzSiiGR5jmIODb+Em 8c4YhfjjFp0Ghu0r8KnyvG0O3GcmUlZ1ZYaA87ikGQ+I4PaufKKLccumJApxw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=Mm8l/URbd+D/cAPgTSxBgpAflZI=; b=pDbn3iOfUnu20LYm/72m 2Lw2xIMEXqyWckw3kDdU09QydzyGWIGPLrj9qkibw4TM51WiUALlaoZRw33lL+tn Ic/ZqVVaLxzb6rSJlyb+9D4NtCsfTtICQ/ltjOCy1BudxuEmMHkJwiQQITILOxrX QZS/PtLnL6+ryxH8Zl1d5V4= Received: (qmail 55897 invoked by alias); 15 Jun 2015 22:15:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 55886 invoked by uid 89); 15 Jun 2015 22:15:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ig0-f177.google.com Received: from mail-ig0-f177.google.com (HELO mail-ig0-f177.google.com) (209.85.213.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 15 Jun 2015 22:15:48 +0000 Received: by igbos3 with SMTP id os3so30343403igb.0 for ; Mon, 15 Jun 2015 15:15:46 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.107.4.204 with SMTP id 195mr38062400ioe.40.1434406546045; Mon, 15 Jun 2015 15:15:46 -0700 (PDT) Received: by 10.36.108.21 with HTTP; Mon, 15 Jun 2015 15:15:45 -0700 (PDT) Date: Mon, 15 Jun 2015 18:15:45 -0400 Message-ID: Subject: [PATCH] Altivec mulv4si3 and mulv8hi3 cleanup From: David Edelsohn To: GCC Patches POWER8 added a multiply instruction that makes mulv4si more efficient. And vmladduhm can be used for mulv8hi3. This patch also changes vmladduhm from a black box UNSPEC to descriptive RTL. Bootstrapped on powerpc64le-linux. * altivec.md: Delete UNSPEC_VMLADDUHM. (mulv4si3_p8): New pattern. (mulv4si3): Use it for POWER8. (mulv8hi3): Use vmladduhm with zero addend. (altivec_vmladduhm): Descriptive RTL. - David * altivec.md: Delete UNSPEC_VMLADDUHM. (mulv4si3_p8): New pattern. (mulv4si3): Use it for POWER8. (mulv8hi3): Use vmladduhm with zero addend. (altivec_vmladduhm): Descriptive RTL. Index: altivec.md =================================================================== --- altivec.md (revision 224450) +++ altivec.md (working copy) @@ -27,7 +27,6 @@ UNSPEC_VMSUMSHS UNSPEC_VMHADDSHS UNSPEC_VMHRADDSHS - UNSPEC_VMLADDUHM UNSPEC_VADDCUW UNSPEC_VADDU UNSPEC_VADDS @@ -634,13 +633,20 @@ ;; [(set (match_operand:V4SI 0 "register_operand" "=v") ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v") ;; (match_operand:V4SI 2 "register_operand" "v")))] +(define_insn "mulv4si3_p8" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (mult:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_P8_VECTOR" + "vmuluwm %0,%1,%2" + [(set_attr "type" "veccomplex")]) + (define_expand "mulv4si3" [(use (match_operand:V4SI 0 "register_operand" "")) (use (match_operand:V4SI 1 "register_operand" "")) (use (match_operand:V4SI 2 "register_operand" ""))] "TARGET_ALTIVEC" - " - { +{ rtx zero; rtx swap; rtx small_swap; @@ -650,6 +656,12 @@ rtx low_product; rtx high_product; + if (TARGET_P8_VECTOR) + { + emit_insn (gen_mulv4si3_p8 (operands[0], operands[1], operands[2])); + DONE; + } + zero = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vspltisw (zero, const0_rtx)); @@ -679,7 +691,7 @@ emit_insn (gen_addv4si3 (operands[0], high_product, low_product)); DONE; - }") +}) (define_expand "mulv8hi3" [(use (match_operand:V8HI 0 "register_operand" "")) @@ -686,32 +698,14 @@ (use (match_operand:V8HI 1 "register_operand" "")) (use (match_operand:V8HI 2 "register_operand" ""))] "TARGET_ALTIVEC" - " { - rtx odd = gen_reg_rtx (V4SImode); - rtx even = gen_reg_rtx (V4SImode); - rtx high = gen_reg_rtx (V4SImode); - rtx low = gen_reg_rtx (V4SImode); + rtx zero = gen_reg_rtx (V8HImode); - if (BYTES_BIG_ENDIAN) - { - emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2])); - emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2])); - emit_insn (gen_altivec_vmrghw_direct (high, even, odd)); - emit_insn (gen_altivec_vmrglw_direct (low, even, odd)); - emit_insn (gen_altivec_vpkuwum_direct (operands[0], high, low)); - } - else - { - emit_insn (gen_altivec_vmulosh (even, operands[1], operands[2])); - emit_insn (gen_altivec_vmulesh (odd, operands[1], operands[2])); - emit_insn (gen_altivec_vmrghw_direct (high, odd, even)); - emit_insn (gen_altivec_vmrglw_direct (low, odd, even)); - emit_insn (gen_altivec_vpkuwum_direct (operands[0], low, high)); - } + emit_insn (gen_altivec_vspltish (zero, const0_rtx)); + emit_insn (gen_altivec_vmladduhm(operands[0], operands[1], operands[2], zero)); DONE; -}") +}) ;; Fused multiply subtract (define_insn "*altivec_vnmsubfp" @@ -851,10 +845,9 @@ (define_insn "altivec_vmladduhm" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V8HI 3 "register_operand" "v")] - UNSPEC_VMLADDUHM))] + (plus:V8HI (mult:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")) + (match_operand:V8HI 3 "register_operand" "v")))] "TARGET_ALTIVEC" "vmladduhm %0,%1,%2,%3" [(set_attr "type" "veccomplex")])