From patchwork Thu Jun 4 10:09:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 480583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B00AF1401B5 for ; Thu, 4 Jun 2015 20:09:43 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=IsLoi6lK; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=ZkZhQNeT+FaKBfkUF+u805HqWC6DoFkBYvoPxwH/dsvSU2 NvfT71JL7flCPDlWCFGrsQjqyTQjQP+XwMLhrSMWnfc+4GzQNH90kx502IWCHirF mph59mp/OJUxku6kAW6QCf0DotjSa26vY6lDSjhQstSv5/CVCvBbwNGDw+dUQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=B6lJJYj92b4KtCekyTlSjEuJ0go=; b=IsLoi6lKJQ/7qt0/939A ByS61slNBIXvl22vOixtRlRWfblPr/4eIchDSPdc/qzyy0hrYaq0CFHBN5Bk3xm9 hS9VluDXkxqaAiVcPjtt0wnxH8siJsiHPWooL66/mXRrJ1ERDtIFFIgyCdrC2byp zfTplgZslHaK3bwSGkWfbD0= Received: (qmail 64455 invoked by alias); 4 Jun 2015 10:09:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 64411 invoked by uid 89); 4 Jun 2015 10:09:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f173.google.com Received: from mail-ob0-f173.google.com (HELO mail-ob0-f173.google.com) (209.85.214.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 04 Jun 2015 10:09:26 +0000 Received: by obbqz1 with SMTP id qz1so10565051obb.3 for ; Thu, 04 Jun 2015 03:09:24 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.28.106 with SMTP id a10mr7828086obh.55.1433412564324; Thu, 04 Jun 2015 03:09:24 -0700 (PDT) Received: by 10.60.147.170 with HTTP; Thu, 4 Jun 2015 03:09:24 -0700 (PDT) Date: Thu, 4 Jun 2015 12:09:24 +0200 Message-ID: Subject: [PATCH, i386]: PR66369, implement zero-extended MOVMSK instructions From: Uros Bizjak To: "gcc-patches@gcc.gnu.org" 2015-06-04 Uros Bizjak PR target/66369 * config/i386/sse.md (_pmovmsk): Merge from avx2_pmovmskb and sse2_pmovmskb using VI1_AVX2 mode iterator. (*_movmsk_zext): New insn pattern. (*_pmovmskb_zext): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 224114) +++ config/i386/sse.md (working copy) @@ -13112,27 +13112,51 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "avx2_pmovmskb" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V32QI 1 "register_operand" "x")] - UNSPEC_MOVMSK))] - "TARGET_AVX2" - "vpmovmskb\t{%1, %0|%0, %1}" +(define_insn "*_movmsk_zext" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(match_operand:VF_128_256 1 "register_operand" "x")] + UNSPEC_MOVMSK)))] + "TARGET_64BIT && TARGET_SSE" + "%vmovmsk\t{%1, %k0|%k0, %1}" [(set_attr "type" "ssemov") - (set_attr "prefix" "vex") - (set_attr "mode" "DI")]) + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "")]) -(define_insn "sse2_pmovmskb" +(define_insn "_pmovmskb" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")] - UNSPEC_MOVMSK))] + (unspec:SI + [(match_operand:VI1_AVX2 1 "register_operand" "x")] + UNSPEC_MOVMSK))] "TARGET_SSE2" "%vpmovmskb\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") - (set_attr "prefix_data16" "1") + (set (attr "prefix_data16") + (if_then_else + (match_test "TARGET_AVX") + (const_string "*") + (const_string "1"))) (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) +(define_insn "*_pmovmskb_zext" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (unspec:SI + [(match_operand:VI1_AVX2 1 "register_operand" "x")] + UNSPEC_MOVMSK)))] + "TARGET_64BIT && TARGET_SSE2" + "%vpmovmskb\t{%1, %k0|%k0, %1}" + [(set_attr "type" "ssemov") + (set (attr "prefix_data16") + (if_then_else + (match_test "TARGET_AVX") + (const_string "*") + (const_string "1"))) + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "SI")]) + (define_expand "sse2_maskmovdqu" [(set (match_operand:V16QI 0 "memory_operand") (unspec:V16QI [(match_operand:V16QI 1 "register_operand")