From patchwork Tue Jul 2 15:52:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1126347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504199-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="DC9oePpU"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f3KBUBlg"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45dTJx5dQDz9s00 for ; Wed, 3 Jul 2019 01:52:32 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=Y9jjUC2FkEQy7QFaFtAMTvENL02i02bu/q31HA6m/F90l1 zroL3JHJ26Vdbdaxe6p5jidUe/MTVhqAch4dOmyegGYTRq+MQ2Mg5wtybHhEgqdZ nRiWkS676MAilge5Srmt118NEjjx4/s+VvZzovSo0BDLXegUVfAHF3uI3J5sk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=5XBG4LeZem8eBID9OXwRUiESugk=; b=DC9oePpUSq1YsAllbgGE /hVo2luI25aE4QrzCh8mO0fo+oPmhSUahHinwgCqmBR9DT9Ye45eUgvl0PoTAKQU ciz+DQYs53ALfHzEOMoJpqx8hdQTGHgtNYi2XZRDBP611aPgirBBj8OwuV6W4R6a 2751sbPypoPE3fetgUrEzLQ= Received: (qmail 96187 invoked by alias); 2 Jul 2019 15:52:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 96176 invoked by uid 89); 2 Jul 2019 15:52:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-io1-f49.google.com Received: from mail-io1-f49.google.com (HELO mail-io1-f49.google.com) (209.85.166.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 02 Jul 2019 15:52:23 +0000 Received: by mail-io1-f49.google.com with SMTP id u19so29563872ior.9 for ; Tue, 02 Jul 2019 08:52:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=t9PHQkSN20SjE3dOVpYnr3VAN1nnSLP0Jx3HR+TCjQk=; b=f3KBUBlgkcri8f60G+vUVq6pannmXqbUlNkJjZ+f/rFTPncm5wijcB0qLw2W5MJmFm jLgColQt8um+QP41F9wxx1R2W3OIRDPW7Jj9N360icPeRz3cEL8Uo9FpNNINWvuHiVQ2 aiycz974sIHY8bNasQ1tXT4GxKkFaS+GlcDgN8tA6SmW55uuRuYyvPD1HwjD4Ak01lBh kQBbLx/Td3AXyzxzGBlbGs10u4dct0owmj6OQS4aFBZXtF29t7biepeB0xGzVcaOKtyt wMRO/kMmLePOO/eKVaGXFgPU73EQQhzZbg9rJcyt1DJ4OVDEtjZNbHN4UU66nhj1INQR m7Tw== MIME-Version: 1.0 From: Uros Bizjak Date: Tue, 2 Jul 2019 17:52:09 +0200 Message-ID: Subject: [PATCH, i386]: Improve split condition for complex MMX with SSE emulations To: "gcc-patches@gcc.gnu.org" Attached patch improves the split condition from using TARGET_MMX_WITH_SSE to TARGET_SSEx && SSE_REGNO_P, which is what these splitters really split. 2019-07-02 Uroš Bizjak * config/i386/mmx.md (mmx_packswb): Use TARGET_SSE2 && SSE_REGNO_P in split condition. (mmx_packssdw): Ditto. (mmx_punpckhbw): Ditto. (mmx_punpcklbw): Ditto. (mmx_punpckhwd): Ditto. (mmx_punpcklwd): Ditto. (mmx_punpckhdq): Ditto. (mmx_punpckldq): Ditto. (*vec_dupv4hi): Ditto. (*vec_dupv2si): Ditto. (mmx_pmovmskb): Ditto. * config/i386/sse.md (sse_cvtpi2ps): Use TARGET_SSE2 && SSE_REG_P in split condition. (ssse3_phwv4hi3): Use TARGET_SSSE3 && SSE_REGNO_P in split condition. (ssse3_phdv2si3): Ditto. (ssse3_pshufbv8qi3): Ditto. (ssse3_palignrdi): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 9ff86ba0eecc..4c71e66e6607 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1228,7 +1228,8 @@ packswb\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_pack (operands, ); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1247,7 +1248,8 @@ packssdw\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1269,7 +1271,8 @@ punpckhbw\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_punpck (operands, true); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1291,7 +1294,8 @@ punpcklbw\t{%2, %0|%0, %k2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_punpck (operands, false); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1311,7 +1315,8 @@ punpckhwd\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_punpck (operands, true); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1331,7 +1336,8 @@ punpcklwd\t{%2, %0|%0, %k2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_punpck (operands, false); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1351,7 +1357,8 @@ punpckhdq\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_punpck (operands, true); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1371,7 +1378,8 @@ punpckldq\t{%2, %0|%0, %k2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] "ix86_split_mmx_punpck (operands, false); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") @@ -1517,7 +1525,8 @@ pshufw\t{$0, %0, %0|%0, %0, 0} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] { rtx op; @@ -1889,7 +1898,8 @@ "@ pmovmskb\t{%1, %0|%0, %1} #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REGNO_P (REGNO (operands[1]))" [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)) (set (match_dup 0) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0494cbf08ac2..8f50cb12c60a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5110,7 +5110,8 @@ cvtpi2ps\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE2 && reload_completed + && SSE_REG_P (operands[2])" [(const_int 0)] { rtx op2 = lowpart_subreg (V4SImode, operands[2], @@ -15881,7 +15882,8 @@ phw\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSSE3 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] { /* Generate SSE version of the operation. */ @@ -15997,7 +15999,8 @@ phd\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSSE3 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] { /* Generate SSE version of the operation. */ @@ -16353,7 +16356,8 @@ pshufb\t{%2, %0|%0, %2} # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSSE3 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(set (match_dup 3) (match_dup 5)) (set (match_dup 3) (and:V4SI (match_dup 3) (match_dup 2))) @@ -16490,7 +16494,8 @@ gcc_unreachable (); } } - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSSE3 && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(set (match_dup 0) (lshiftrt:V1TI (match_dup 0) (match_dup 3)))] {