diff mbox series

i386: Fix ix86_hard_regno_mode_ok for TDmode on 32bit targets [PR101346]

Message ID CAFULd4b97nMqZX07jvOrezKtpNrypLmvxpT5ZG38e_-t-fHHPA@mail.gmail.com
State New
Headers show
Series i386: Fix ix86_hard_regno_mode_ok for TDmode on 32bit targets [PR101346] | expand

Commit Message

Uros Bizjak July 15, 2021, 8:43 p.m. UTC 
General regs on 32bit targets do not support 128bit modes,
including TDmode.

gcc/

2021-07-15  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/101346
    * config/i386/i386.h (VALID_SSE_REG_MODE): Add TDmode.
    (VALID_INT_MODE_P): Add SDmode and DDmode.
    Add TDmode for TARGET_64BIT.
    (VALID_DFP_MODE_P): Remove.
    * config/i386/i386.c (ix86_hard_regno_mode_ok):
    Do not use VALID_DFP_MODE_P.

gcc/testsuite/

2021-07-15  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/101346
    * gcc.target/i386/pr101346.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Pushed to master.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 530d3572965..9d74b7a191b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -19535,11 +19535,8 @@  ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
       return !can_create_pseudo_p ();
     }
   /* We handle both integer and floats in the general purpose registers.  */
-  else if (VALID_INT_MODE_P (mode))
-    return true;
-  else if (VALID_FP_MODE_P (mode))
-    return true;
-  else if (VALID_DFP_MODE_P (mode))
+  else if (VALID_INT_MODE_P (mode)
+	   || VALID_FP_MODE_P (mode))
     return true;
   /* Lots of MMX code casts 8 byte vector modes to DImode.  If we then go
      on to use that value in smaller contexts, this can easily force a
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 324e8a952d9..0c2c93daf32 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1023,7 +1023,7 @@  extern const char *host_detect_local_cpu (int argc, const char **argv);
 #define VALID_SSE_REG_MODE(MODE)					\
   ((MODE) == V1TImode || (MODE) == TImode				\
    || (MODE) == V4SFmode || (MODE) == V4SImode				\
-   || (MODE) == SFmode || (MODE) == TFmode)
+   || (MODE) == SFmode || (MODE) == TFmode || (MODE) == TDmode)
 
 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
   ((MODE) == V2SFmode || (MODE) == SFmode)
@@ -1037,9 +1037,6 @@  extern const char *host_detect_local_cpu (int argc, const char **argv);
 
 #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
 
-#define VALID_DFP_MODE_P(MODE) \
-  ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
-
 #define VALID_FP_MODE_P(MODE)						\
   ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode		\
    || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)		\
@@ -1049,12 +1046,13 @@  extern const char *host_detect_local_cpu (int argc, const char **argv);
    || (MODE) == SImode || (MODE) == DImode				\
    || (MODE) == CQImode || (MODE) == CHImode				\
    || (MODE) == CSImode || (MODE) == CDImode				\
+   || (MODE) == SDmode || (MODE) == DDmode				\
    || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode	\
    || (TARGET_64BIT							\
        && ((MODE) == TImode || (MODE) == CTImode			\
 	   || (MODE) == TFmode || (MODE) == TCmode			\
 	   || (MODE) == V8QImode || (MODE) == V4HImode			\
-	   || (MODE) == V2SImode)))
+	   || (MODE) == V2SImode || (MODE) == TDmode)))
 
 /* Return true for modes passed in SSE registers.  */
 #define SSE_REG_MODE_P(MODE)						\
diff --git a/gcc/testsuite/gcc.target/i386/pr101346.c b/gcc/testsuite/gcc.target/i386/pr101346.c
new file mode 100644
index 00000000000..fefabaf0e56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101346.c
@@ -0,0 +1,10 @@ 
+/* PR target/101346 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -fprofile-generate -msse" } */
+/* { dg-require-profiling "-fprofile-generate" } */
+
+_Decimal128
+foo (_Decimal128 x)
+{
+  return - __builtin_fabsd128 (x);
+}