From patchwork Sun Aug 21 19:06:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 661278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sHR543tb4z9stY for ; Mon, 22 Aug 2016 05:06:30 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=SYEjuULe; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=aoIwr+88A/gHMCtFvf11OvkZL3ckTClnvDkWB5t244X JuGWOqM/+R3MVfVF4KorstV4orthwMBNhpeVorsZEfSQhf9QfrpESk/tv1CQyoRH MjSIXirn1m1gi790R1EKun9s0bPpC0NJXaVEXtQOCIlgMxPX7FusBY9xkkrrMt88 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=bDQFI9/8XJvKqj+C6C/R1yICh1U=; b=SYEjuULe6x698Z80z PQ2EewZ1gR4D1wi02gL26f7JSJkksbvDzZOMD91cKIh7u5As/pc9UZIYK4QHiRe9 aROrx+Msn8ptT9+kp7u2vXkom7OhJOeJz+9QblvFe8L08ou0fj9gP7z7UluGSMXH RVNS1kawBavuwStOEkhGzbGkFc= Received: (qmail 11832 invoked by alias); 21 Aug 2016 19:06:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 11819 invoked by uid 89); 21 Aug 2016 19:06:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL, BAYES_05, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=TARGET_SSE2, target_sse2, ubizjak@gmail.com, ubizjakgmailcom X-HELO: mail-ua0-f182.google.com Received: from mail-ua0-f182.google.com (HELO mail-ua0-f182.google.com) (209.85.217.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 21 Aug 2016 19:06:11 +0000 Received: by mail-ua0-f182.google.com with SMTP id 97so156432971uav.3 for ; Sun, 21 Aug 2016 12:06:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=pVXG3bnnYPYBFyigqjO/KiBd4oWxt6sHT7LIS4x7dxE=; b=jwQqDNxmh4F9UgcOavq8+74DnSrmOVN8ykK/ytPpHNUhasQCU2RxGCy0GEkCSHhhVX ZYOoHrJNDRZb6r8WWo/0Z0GE8iYK81NfBjtkTQ2qJ8j66oHdPPhMbKCOzEXVlSq9JJNU U7c+jg+n2zDbEvpiNJaGier26b2Bx2jzoY97ETuHanRBVDMTLTE7mpt9R/x/Ush0kHSv CDVDyGbRB/IOvCG7/Ec+Qc3L5hQcYjx6a1oUVpSlYnoF3JoQ0hbcWJkH+zE5lR24pYnr pKaY0frcpHIpqCWerSh2QaKcucQmTplFQEpJFg/gs4l/4aRVVRiqsXdN0fV1J6ni26H1 HaHQ== X-Gm-Message-State: AEkoouvskIuVrl2AO6Mg2jpoedrL1V0pfHXN8+uV+rNJkpYNmEoIMbpNxSfdE/kGQ9j6sjDezj9KmcE0ANJCqg== X-Received: by 10.159.41.231 with SMTP id s94mr9406279uas.58.1471806369395; Sun, 21 Aug 2016 12:06:09 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.21.134 with HTTP; Sun, 21 Aug 2016 12:06:08 -0700 (PDT) From: Uros Bizjak Date: Sun, 21 Aug 2016 21:06:08 +0200 Message-ID: Subject: [PATCH, i386]: Fine tune prefetchw emission (PR 77270) To: "gcc-patches@gcc.gnu.org" Cc: "Kumar, Venkataramanan" , NightStrike StrikeNight Hello! Attached patch fine-tunes the condition when prefetchw write prefetch insns are emitted. prefetchw is preferred for non-SSE2 K7 athlons (this is covered by i386-prefetch.exp tests), on the other hand, SSE prefetches are preferred for K8 targets, as measured and reported in PR 77270. For newer targets, PRFCHW cpuid bit is respected, and -march=native correctly emits prefetchw, when PRFCHW cpuid bit is set. (on a related note, PTA_PRFCHW should probably be set for amdfam10+ targets, Venkataramanan is looking into this issue). 2016-08-21 Uros Bizjak PR target/77270 * config/i386/i386.md (prefetch): When TARGET_PRFCHW or TARGET_PREFETCHWT1 are disabled, emit 3dNOW! write prefetches for non-SSE2 athlons only, otherwise prefer SSE prefetches. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: i386.md =================================================================== --- i386.md (revision 239642) +++ i386.md (working copy) @@ -18634,20 +18634,24 @@ gcc_assert (IN_RANGE (locality, 0, 3)); /* Use 3dNOW prefetch in case we are asking for write prefetch not - supported by SSE counterpart or the SSE prefetch is not available - (K6 machines). Otherwise use SSE prefetch as it allows specifying - of locality. */ + supported by SSE counterpart (non-SSE2 athlon machines) or the + SSE prefetch is not available (K6 machines). Otherwise use SSE + prefetch as it allows specifying of locality. */ if (write) { if (TARGET_PREFETCHWT1) operands[2] = GEN_INT (MAX (locality, 2)); - else if (TARGET_3DNOW || TARGET_PRFCHW) + else if (TARGET_PRFCHW) operands[2] = GEN_INT (3); + else if (TARGET_3DNOW && !TARGET_SSE2) + operands[2] = GEN_INT (3); + else if (TARGET_PREFETCH_SSE) + operands[1] = const0_rtx; else { - gcc_assert (TARGET_PREFETCH_SSE); - operands[1] = const0_rtx; + gcc_assert (TARGET_3DNOW); + operands[2] = GEN_INT (3); } } else