From patchwork Thu Oct 6 08:09:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 678773 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sqQKv4fSFz9sD5 for ; Thu, 6 Oct 2016 19:09:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=uX5DEW3R; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=bklnDA+WD2IGDic3cbr+3XdkzAsdZZfK2xOZkgjIPwh TqLAO/cej4R9n0lSqazhU1iY4HJjeTWBviY+32A+PCW51XgUb+qmRntjrgYb/uKM M/NsrOasYpJc26W6Oi4RCffGwoxkY64VuCuSIbIndoqUOvssaB2i4F1onW6JKuJ0 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=QgozfS8XjPd4Y6kYoW1wv74grU0=; b=uX5DEW3Ry8ijY7z6c adffTb/fK1EhygXvsjIYKGADtumb+m33b+tu4W+UlcShB5yYBt+kU+vrsGz+PhEt S4zCjS7J2OlBOQPgBIQpipnCyLvU5ybp0NnXwX2C/gn9y53jPdXm8yb7bGBFt6oD YixBH1/LhgyYztXNa9X9haJcQU= Received: (qmail 29424 invoked by alias); 6 Oct 2016 08:09:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 29389 invoked by uid 89); 6 Oct 2016 08:09:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=3.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=ubizjak@gmail.com, ubizjakgmailcom, 2016-10-06 X-HELO: mail-ua0-f174.google.com Received: from mail-ua0-f174.google.com (HELO mail-ua0-f174.google.com) (209.85.217.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 06 Oct 2016 08:09:16 +0000 Received: by mail-ua0-f174.google.com with SMTP id r64so10678617uar.3 for ; Thu, 06 Oct 2016 01:09:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=OgHcA3+ZSoAfHHuXRxkev7tYj+fyBxss+UIyoYw6MJE=; b=hO9L5Mxt0jmK37yaZpEXaOacyB1Khvf9VLy6loHxT08Omtwj/LnrgATKdLM1CKiET5 uTEt3iPaci9QHKIqXNYthxcKvZgRjWgGCtSxu2EkaLMrlRDV/bc3fKdPwexMW84ET286 MfQ13eUZof0Lf0093YsVz+YJB5lfpRGcd5USvFKCSSfQWonWD2IMXvTU5rJESSUS8/pt OKW7OKeTV4NZqRgMOEIfVsWX34M2Pj1Ucqu++r6oSLG1jzuLPRZyzbQe21I/kB2d6uxV 3GnJwUTRr4uWcZLrDwM1i+Nv3aM2ysKDw3/rSyrsEHUHMmlJWY7/oW9y5c94BY7nmFHM Ahxw== X-Gm-Message-State: AA6/9RmAU4Sep7JSrZqPaBGzeMF2h7KYXG7JgPlaXL2Trn2CaRLQiRV2Z7AXP5rfyXrSFRyZVFSxFByVsAcM5w== X-Received: by 10.176.1.75 with SMTP id 69mr9938924uak.4.1475741354399; Thu, 06 Oct 2016 01:09:14 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.113.6 with HTTP; Thu, 6 Oct 2016 01:09:13 -0700 (PDT) From: Uros Bizjak Date: Thu, 6 Oct 2016 10:09:13 +0200 Message-ID: Subject: [PATCH, i386]: Remove remaining -Wimplicit-fallthrough warnings from sse.md To: "gcc-patches@gcc.gnu.org" Cc: Jakub Jelinek ... and introduce some related cleanups. 2016-10-06 Uros Bizjak * config/i386/sse.md (andnot3): Add FALLTHRU comments. Introduce ssesuffix variable. (3): Ditto. (*3): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Will commit later today. Uros. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 240814) +++ config/i386/sse.md (working copy) @@ -11263,15 +11263,19 @@ static char buf[64]; const char *ops; const char *tmp; + const char *ssesuffix; switch (get_attr_mode (insn)) { case MODE_XI: gcc_assert (TARGET_AVX512F); + /* FALLTHRU */ case MODE_OI: gcc_assert (TARGET_AVX2); + /* FALLTHRU */ case MODE_TI: gcc_assert (TARGET_SSE2); + tmp = "pandn"; switch (mode) { case V64QImode: @@ -11278,31 +11282,33 @@ case V32HImode: /* There is no vpandnb or vpandnw instruction, nor vpandn for 512-bit vectors. Use vpandnq instead. */ - tmp = "pandnq"; + ssesuffix = "q"; break; case V16SImode: case V8DImode: - tmp = "pandn"; + ssesuffix = ""; break; case V8SImode: case V4DImode: case V4SImode: case V2DImode: - tmp = TARGET_AVX512VL ? "pandn" : "pandn"; + ssesuffix = TARGET_AVX512VL ? "" : ""; break; default: - tmp = TARGET_AVX512VL ? "pandnq" : "pandn"; - break; + ssesuffix = TARGET_AVX512VL ? "q" : ""; } break; case MODE_V16SF: gcc_assert (TARGET_AVX512F); + /* FALLTHRU */ case MODE_V8SF: gcc_assert (TARGET_AVX); + /* FALLTHRU */ case MODE_V4SF: gcc_assert (TARGET_SSE); - tmp = "andnps"; + tmp = "andn"; + ssesuffix = "ps"; break; default: @@ -11312,16 +11318,16 @@ switch (which_alternative) { case 0: - ops = "%s\t{%%2, %%0|%%0, %%2}"; + ops = "%s%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v%s%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), ops, tmp); + snprintf (buf, sizeof (buf), ops, tmp, ssesuffix); return buf; } [(set_attr "isa" "noavx,avx") @@ -11387,6 +11393,7 @@ static char buf[64]; const char *ops; const char *tmp; + const char *ssesuffix; switch (get_attr_mode (insn)) { @@ -11398,17 +11405,18 @@ /* FALLTHRU */ case MODE_TI: gcc_assert (TARGET_SSE2); + tmp = "p"; switch (mode) { case V16SImode: case V8DImode: - tmp = "p"; + ssesuffix = ""; break; case V8SImode: case V4DImode: case V4SImode: case V2DImode: - tmp = TARGET_AVX512VL ? "p" : "p"; + ssesuffix = TARGET_AVX512VL ? "" : ""; break; default: gcc_unreachable (); @@ -11417,9 +11425,11 @@ case MODE_V8SF: gcc_assert (TARGET_AVX); + /* FALLTHRU */ case MODE_V4SF: gcc_assert (TARGET_SSE); - tmp = "ps"; + tmp = ""; + ssesuffix = "ps"; break; default: @@ -11430,18 +11440,18 @@ { case 0: if () - ops = "v%s\t{%%2, %%0, %%0|%%0, %%0, %%2}"; + ops = "v%s%s\t{%%2, %%0, %%0|%%0, %%0, %%2}"; else - ops = "%s\t{%%2, %%0|%%0, %%2}"; + ops = "%s%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v%s%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), ops, tmp); + snprintf (buf, sizeof (buf), ops, tmp, ssesuffix); return buf; } [(set_attr "isa" "noavx,avx") @@ -11492,11 +11502,11 @@ /* FALLTHRU */ case MODE_TI: gcc_assert (TARGET_SSE2); + tmp = "p"; switch (mode) { case V64QImode: case V32HImode: - tmp = "p"; ssesuffix = "q"; break; case V32QImode: @@ -11503,7 +11513,6 @@ case V16HImode: case V16QImode: case V8HImode: - tmp = "p"; ssesuffix = TARGET_AVX512VL ? "q" : ""; break; default: @@ -11513,10 +11522,11 @@ case MODE_V8SF: gcc_assert (TARGET_AVX); + /* FALLTHRU */ case MODE_V4SF: gcc_assert (TARGET_SSE); - tmp = "ps"; - ssesuffix = ""; + tmp = ""; + ssesuffix = "ps"; break; default: @@ -11526,17 +11536,16 @@ switch (which_alternative) { case 0: - ops = "%s\t{%%2, %%0|%%0, %%2}"; - snprintf (buf, sizeof (buf), ops, tmp); + ops = "%s%s\t{%%2, %%0|%%0, %%2}"; break; case 1: ops = "v%s%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; - snprintf (buf, sizeof (buf), ops, tmp, ssesuffix); break; default: gcc_unreachable (); } + snprintf (buf, sizeof (buf), ops, tmp, ssesuffix); return buf; } [(set_attr "isa" "noavx,avx")