From patchwork Sat Oct 29 17:51:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 122545 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 07BACB6F69 for ; Sun, 30 Oct 2011 04:52:00 +1100 (EST) Received: (qmail 18974 invoked by alias); 29 Oct 2011 17:51:58 -0000 Received: (qmail 18966 invoked by uid 22791); 29 Oct 2011 17:51:56 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_ZJ, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-gy0-f175.google.com (HELO mail-gy0-f175.google.com) (209.85.160.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 29 Oct 2011 17:51:41 +0000 Received: by gyd8 with SMTP id 8so483248gyd.20 for ; Sat, 29 Oct 2011 10:51:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.147.29.3 with SMTP id g3mr1535016yaj.30.1319910700690; Sat, 29 Oct 2011 10:51:40 -0700 (PDT) Received: by 10.147.114.16 with HTTP; Sat, 29 Oct 2011 10:51:40 -0700 (PDT) Date: Sat, 29 Oct 2011 19:51:40 +0200 Message-ID: Subject: [PATCH, i386]: Remove lshlv16qi3 and add lshrv16qi3 XOP expander From: Uros Bizjak To: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! lshlv16qi3 is not a generic name for expander, and we have ashlv16qi3 for this. Attached patch adds lshrv16qi3 to generate logical shift-right XOP instruction. 2011-10-29 Uros Bizjak * config/i386/i386.md (lshlv16qi3): Remove expander. (lshrv16qi3): New expander. (v16qi3): Macroize expander from ashrv16qi3 and lshrv16qi3 using any_shiftrt code iterator. Cleanup. (ashlv16qi3): Cleanup. (ashrv2di3): Ditto. Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32} and committed to SVN mainline. Uros. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 180650) +++ config/i386/sse.md (working copy) @@ -11382,7 +11385,7 @@ (set_attr "prefix_extra" "2") (set_attr "mode" "TI")]) -;; SSE2 doesn't have some shift varients, so define versions for XOP +;; SSE2 doesn't have some shift variants, so define versions for XOP (define_expand "ashlv16qi3" [(set (match_operand:V16QI 0 "register_operand" "") (ashift:V16QI @@ -11390,65 +11393,52 @@ (match_operand:SI 2 "nonmemory_operand" "")))] "TARGET_XOP" { - rtvec vs = rtvec_alloc (16); - rtx par = gen_rtx_PARALLEL (V16QImode, vs); rtx reg = gen_reg_rtx (V16QImode); + rtx par; int i; + + par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16)); for (i = 0; i < 16; i++) - RTVEC_ELT (vs, i) = operands[2]; + XVECEXP (par, 0, i) = operands[2]; emit_insn (gen_vec_initv16qi (reg, par)); emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg)); DONE; }) -(define_expand "lshlv16qi3" - [(match_operand:V16QI 0 "register_operand" "") - (match_operand:V16QI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")] - "TARGET_XOP" -{ - rtvec vs = rtvec_alloc (16); - rtx par = gen_rtx_PARALLEL (V16QImode, vs); - rtx reg = gen_reg_rtx (V16QImode); - int i; - for (i = 0; i < 16; i++) - RTVEC_ELT (vs, i) = operands[2]; - - emit_insn (gen_vec_initv16qi (reg, par)); - emit_insn (gen_xop_lshlv16qi3 (operands[0], operands[1], reg)); - DONE; -}) - -(define_expand "ashrv16qi3" +(define_expand "v16qi3" [(set (match_operand:V16QI 0 "register_operand" "") - (ashiftrt:V16QI + (any_shiftrt:V16QI (match_operand:V16QI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "TARGET_XOP" { - rtvec vs = rtvec_alloc (16); - rtx par = gen_rtx_PARALLEL (V16QImode, vs); rtx reg = gen_reg_rtx (V16QImode); + rtx par; + bool negate = false; + rtx (*shift_insn)(rtx, rtx, rtx); int i; - rtx ele = ((CONST_INT_P (operands[2])) - ? GEN_INT (- INTVAL (operands[2])) - : operands[2]); + if (CONST_INT_P (operands[2])) + operands[2] = GEN_INT (-INTVAL (operands[2])); + else + negate = true; + + par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16)); for (i = 0; i < 16; i++) - RTVEC_ELT (vs, i) = ele; + XVECEXP (par, 0, i) = operands[2]; emit_insn (gen_vec_initv16qi (reg, par)); - if (!CONST_INT_P (operands[2])) - { - rtx neg = gen_reg_rtx (V16QImode); - emit_insn (gen_negv16qi2 (neg, reg)); - emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], neg)); - } + if (negate) + emit_insn (gen_negv16qi2 (reg, reg)); + + if ( == LSHIFTRT) + shift_insn = gen_xop_lshlv16qi3; else - emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg)); + shift_insn = gen_xop_ashlv16qi3; + emit_insn (shift_insn (operands[0], operands[1], reg)); DONE; }) @@ -11459,29 +11449,25 @@ (match_operand:DI 2 "nonmemory_operand" "")))] "TARGET_XOP" { - rtvec vs = rtvec_alloc (2); - rtx par = gen_rtx_PARALLEL (V2DImode, vs); rtx reg = gen_reg_rtx (V2DImode); - rtx ele; + rtx par; + bool negate = false; + int i; if (CONST_INT_P (operands[2])) - ele = GEN_INT (- INTVAL (operands[2])); - else if (GET_MODE (operands[2]) != DImode) - { - rtx move = gen_reg_rtx (DImode); - ele = gen_reg_rtx (DImode); - convert_move (move, operands[2], false); - emit_insn (gen_negdi2 (ele, move)); - } + operands[2] = GEN_INT (-INTVAL (operands[2])); else - { - ele = gen_reg_rtx (DImode); - emit_insn (gen_negdi2 (ele, operands[2])); - } + negate = true; - RTVEC_ELT (vs, 0) = ele; - RTVEC_ELT (vs, 1) = ele; + par = gen_rtx_PARALLEL (V2DImode, rtvec_alloc (2)); + for (i = 0; i < 2; i++) + XVECEXP (par, 0, i) = operands[2]; + emit_insn (gen_vec_initv2di (reg, par)); + + if (negate) + emit_insn (gen_negv2di2 (reg, reg)); + emit_insn (gen_xop_ashlv2di3 (operands[0], operands[1], reg)); DONE; })