From patchwork Thu Jun 16 16:09:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 636548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rVpJ74WQ6z9t0f for ; Fri, 17 Jun 2016 02:10:14 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=jvu45p5O; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=qZRH4vLvi1/HGeR hfLGu78M95NHFJ5s9OJDYGNNlr5A6e5lHghaz47URP6vqTFnXqWMvyopU/mcwBU7 TR5gudMEc39KyA4arDvskDLDDoBzZHuf+9XmAPSONkf24Y4S3V2iTiIIWSdQOQNN rL8w/fgeAzyDRsWHjeLY8fZ5LEO4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; s=default; bh=rrrMr5ZEqq2KbkJudO2MX /ITgEY=; b=jvu45p5OQ18AwpjaHxvC0J1mpG71L/63s+simqrEcFLuxWkTAbuKi RVGKiGp2yqy6O7pJw68hKGBOCUQNSqm6b9hw1OBcBMUXEE5vQ5euzM1InVD/bnAZ jeSMePYZ/zeEO4CaBb7B/rQem/A8My2WNmOwoVNVIjSiKUGQQwSyi8= Received: (qmail 27771 invoked by alias); 16 Jun 2016 16:10:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 27760 invoked by uid 89); 16 Jun 2016 16:10:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.2 required=5.0 tests=AWL, BAYES_80, FREEMAIL_FROM, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 spammy=nano, esther, samuel, Samuel X-HELO: mail-vk0-f66.google.com Received: from mail-vk0-f66.google.com (HELO mail-vk0-f66.google.com) (209.85.213.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 16 Jun 2016 16:09:49 +0000 Received: by mail-vk0-f66.google.com with SMTP id k2so8915326vkb.0 for ; Thu, 16 Jun 2016 09:09:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=aivgObYTiyw65R96r4t/73LNG0Bhm/wvOj41Ny6yPFY=; b=DQ3prYYGIhlshxVJXH0vG3cvs8XpIdzrMmK/wO4PKfR0m2AiNjDy8KUZwnhc6l3T+X vomyW4+/jvE6KWclM90OzlfHb+2oX/Lr5op6O/xzOqUk0AKZBmyVfoSv0rjMc0JqhZkj upIFtDmAFkOUbbT+3bAZNnure+9pnnWFPsm35BhlbvZhYom6fXQmqd3fQ9ePfZ1uvGNG Alv9CTqpKAt71+/vM/ftdWXjejcZbdOFuh71FNubcsjleBAxhPD9QHwUODX5ASyazOq1 2NhrkFLQNsV7itJn6KmnjpFbw6M5zDFgWGbCH/Y7J7tNS0YKmdJjAiZUkQVUDW8Kow6l /BLg== X-Gm-Message-State: ALyK8tLzzVsX509oXOw6dIAot3/G/giq4w9c8NIZ19dtX4okGtJfBgJQQNO76zBzuxNv5gnYUA6N/5ppYH+kHg== X-Received: by 10.176.6.41 with SMTP id f38mr2387583uaf.82.1466093386650; Thu, 16 Jun 2016 09:09:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.19.198 with HTTP; Thu, 16 Jun 2016 09:09:45 -0700 (PDT) In-Reply-To: <1466068324.17643.124.camel@magic.fr> References: <1466068324.17643.124.camel@magic.fr> From: Uros Bizjak Date: Thu, 16 Jun 2016 18:09:45 +0200 Message-ID: Subject: Re: [PATCH, i386][Updated] Add native support for VIA C7, Eden and Nano CPUs To: "J. Mayer" Cc: "gcc-patches@gcc.gnu.org" On Thu, Jun 16, 2016 at 11:12 AM, J. Mayer wrote: > The following patch adds support and native detection for C7, Eden > "Samuel2", Eden "Nehemiah", Eden "Esther", Eden x2, Eden x4, Nano 1xxx, > Nano 2xxx, Nano 3xxx, Nano x2 and Nano x4 VIA CPUs. > > This patch has been updated against current repository. > It contains documentation and Changelog updates. > > Please CC me to any comment / review / change request. The patch is OK, modulo redundant : Pass c7, nehemiah or samuel-2 for signature_CENTAUR_ebx. The should not be reached for new processors. This part is a safety net, intended for "strange" targets - emulators, prehistoric parts or simply for the cases where the precise details shouldn't matter. Attached is the patch I have committed to SVN repository. 2016-06-16 Jocelyn Mayer * config/i386/driver-i386.c (host_detect_local_cpu): Set PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode. : Pass nano-3000, nano, eden-x2 or k8 for signature_CENTAUR_ebx. * config/i386/i386.c (ix86_option_override_internal): Add definitions for VIA c7, samuel-2, nehemiah, esther, eden-x2, eden-x4, nano, nano-1000, nano-2000, nano-3000, nano-x2 and nano-x4. * doc/invoke.texi: Document new VIA -march entries. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}, committed to mainline. BTW: Can you please prepare an entry for the release notes (something like [1]) mentioning new options? (Release notes are not yet present for 7.0 development branch, so there is quite some time available ;) ) [1] https://gcc.gnu.org/gcc-6/changes.html Uros. Index: config/i386/driver-i386.c =================================================================== --- config/i386/driver-i386.c (revision 237528) +++ config/i386/driver-i386.c (working copy) @@ -651,7 +651,9 @@ break; case 6: - if (model > 9 || has_longmode) + if (has_longmode) + processor = PROCESSOR_K8; + else if (model > 9) /* Use the default detection procedure. */ ; else if (model == 9) @@ -869,9 +871,30 @@ cpu = "athlon"; break; case PROCESSOR_K8: - if (arch && has_sse3) - cpu = "k8-sse3"; + if (arch) + { + if (vendor == signature_CENTAUR_ebx) + { + if (has_sse4_1) + /* Nano 3000 | Nano dual / quad core | Eden X4 */ + cpu = "nano-3000"; + else if (has_ssse3) + /* Nano 1000 | Nano 2000 */ + cpu = "nano"; + else if (has_sse3) + /* Eden X2 */ + cpu = "eden-x2"; + else + /* Default to k8 */ + cpu = "k8"; + } + else if (has_sse3) + cpu = "k8-sse3"; + else + cpu = "k8"; + } else + /* For -mtune, we default to -mtune=k8 */ cpu = "k8"; break; case PROCESSOR_AMDFAM10: Index: config/i386/i386.c =================================================================== --- config/i386/i386.c (revision 237528) +++ config/i386/i386.c (working copy) @@ -4783,8 +4783,15 @@ {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX}, {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, + {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_FXSR}, + {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, + PTA_MMX | PTA_SSE | PTA_FXSR}, + {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, + PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR}, + {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, + PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR}, {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR}, @@ -4843,6 +4850,29 @@ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR}, {"x86-64", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR}, + {"eden-x2", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR}, + {"nano", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_FXSR}, + {"nano-1000", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_FXSR}, + {"nano-2000", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_FXSR}, + {"nano-3000", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, + {"nano-x2", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, + {"eden-x4", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, + {"nano-x4", PROCESSOR_K8, CPU_K8, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR}, {"k8", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, Index: doc/invoke.texi =================================================================== --- doc/invoke.texi (revision 237528) +++ doc/invoke.texi (working copy) @@ -23357,14 +23357,68 @@ instruction set support. @item c3 -VIA C3 CPU with MMX and 3DNow!@: instruction set support. (No scheduling is -implemented for this chip.) +VIA C3 CPU with MMX and 3DNow!@: instruction set support. +(No scheduling is implemented for this chip.) @item c3-2 VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support. -(No scheduling is -implemented for this chip.) +(No scheduling is implemented for this chip.) +@item c7 +VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item samuel-2 +VIA Eden Samuel 2 CPU with MMX and 3DNow!@: instruction set support. +(No scheduling is implemented for this chip.) + +@item nehemiah +VIA Eden Nehemiah CPU with MMX and SSE instruction set support. +(No scheduling is implemented for this chip.) + +@item esther +VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x2 +VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x4 +VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, +AVX and AVX2 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano +Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-1000 +VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-2000 +VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-3000 +VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x2 +VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 +instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x4 +VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 +instruction set support. +(No scheduling is implemented for this chip.) + @item geode AMD Geode embedded processor with MMX and 3DNow!@: instruction set support. @end table