From patchwork Fri May 7 15:18:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1475578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=hdWRC/CB; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FcDc15f2Nz9sW7 for ; Sat, 8 May 2021 01:18:24 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 11B5C383301D; Fri, 7 May 2021 15:18:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 11B5C383301D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1620400702; bh=vJKcPX6QSfTQxASTHrroWJr9SV/nwyF4WvEVHj1Hbq8=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=hdWRC/CB7cvmT+FhRigfemPi/9yXm0GPNUYlG8c5EUCb1vLcZwzXHrmnU+bAKp3Ch tto4uoQpGl4YGl54lShQnWgEAhAbhTALrAskW9IK4s1tbKeehTUCPvRGrzpYpr/cJ+ hpRtOjDCxXd5wwybIrV+f3b5NkqSdQhRrqkHhXCg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by sourceware.org (Postfix) with ESMTPS id C4180385383A for ; Fri, 7 May 2021 15:18:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org C4180385383A Received: by mail-qk1-x72c.google.com with SMTP id q136so8746010qka.7 for ; Fri, 07 May 2021 08:18:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=vJKcPX6QSfTQxASTHrroWJr9SV/nwyF4WvEVHj1Hbq8=; b=OCvMc8Z06aApra29c6oFgsgrBrUBbWKAgoVCcC0Lyr7m8iTCW2wtXUKj+N9aLgy1gd exikOUma8pQ6CfwHGkNdg2xCqMuh9+0yyBwP8fCM+gHZMcUq3midq4G4k5ExWEl/i+RE vU7EVu+OJeRMxPgbiJoPUJNPZluZ+6fYvdAHPCihjMWFSujwU03gFJdqx8eF6RydcZd7 /nHjyWKELVm+AM+sEVoJGWkAAx/E8N07zKJ4CjdAXti1xBwqFa+svcviSMyikExMSR2J MlWMPj8bOXaJin0+60bJ+5R+yIo0rtVzIyPNDYzeKTaGiCkk1E3gLirbMc/058og/RF4 rlQQ== X-Gm-Message-State: AOAM533waQSKiCT3YSy5GmFESmhi//Rab+D58XS08CTHpUFW3CPqgtDC Y9QisriH+FW0/FxzKm50wve845Q+ZhQ3yaJvesuIUXvq4rQcTg== X-Google-Smtp-Source: ABdhPJyK1OmTZHjjHJjII9EYs23EtWJe9ngDs+mwaXG5gmmOlAOmga4bG6pnS1yGmT3ec2cRPbFrUA8gkl2dcLN4MoM= X-Received: by 2002:ae9:e706:: with SMTP id m6mr169078qka.74.1620400698192; Fri, 07 May 2021 08:18:18 -0700 (PDT) MIME-Version: 1.0 Date: Fri, 7 May 2021 17:18:07 +0200 Message-ID: Subject: [PATCH] i386: Implement mmx_pblendv to optimize SSE conditional moves [PR98218] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Implement mmx_pblendv to optimize V8HI, V4HI and V2SI mode conditional moves for SSE4.1 targets. 2021-05-07 Uroš Bizjak gcc/ PR target/98218 * config/i386/i386-expand.c (ix86_expand_sse_movcc): Handle V8QI, V4HI and V2SI modes. * config/i386/mmx.md (mmx_pblendvb): New insn pattern. * config/i386/sse.md (unspec): Move UNSPEC_BLENDV ... * config/i386/i386.md (unspec): ... here. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 61b2f921f41..e9f11bca78a 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -3702,6 +3702,19 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) op_true = force_reg (mode, op_true); } break; + case E_V8QImode: + case E_V4HImode: + case E_V2SImode: + if (TARGET_SSE4_1) + { + gen = gen_mmx_pblendvb; + if (mode != V8QImode) + d = gen_reg_rtx (V8QImode); + op_false = gen_lowpart (V8QImode, op_false); + op_true = gen_lowpart (V8QImode, op_true); + cmp = gen_lowpart (V8QImode, cmp); + } + break; case E_V16QImode: case E_V8HImode: case E_V4SImode: diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f79fd122f56..74e924f3c04 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -118,6 +118,7 @@ (define_c_enum "unspec" [ UNSPEC_FIX_NOTRUNC UNSPEC_MASKMOV UNSPEC_MOVMSK + UNSPEC_BLENDV UNSPEC_RCP UNSPEC_RSQRT UNSPEC_PSADBW diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 295501dec2f..f08570856f9 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1700,6 +1700,26 @@ (define_expand "vcond_mask_" DONE; }) +(define_insn "mmx_pblendvb" + [(set (match_operand:V8QI 0 "register_operand" "=Yr,*x,x") + (unspec:V8QI + [(match_operand:V8QI 1 "register_operand" "0,0,x") + (match_operand:V8QI 2 "register_operand" "Yr,*x,x") + (match_operand:V8QI 3 "register_operand" "Yz,Yz,x")] + UNSPEC_BLENDV))] + "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" + "@ + pblendvb\t{%3, %2, %0|%0, %2, %3} + pblendvb\t{%3, %2, %0|%0, %2, %3} + vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "*,*,1") + (set_attr "prefix" "orig,orig,vex") + (set_attr "btver2_decode" "vector") + (set_attr "mode" "TI")]) + ;; XOP parallel XMM conditional moves (define_insn "*xop_pcmov_" [(set (match_operand:MMXMODEI 0 "register_operand" "=x") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 897cf3eaea9..244fb13e97a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -39,7 +39,6 @@ (define_c_enum "unspec" [ UNSPEC_INSERTQ ;; For SSE4.1 support - UNSPEC_BLENDV UNSPEC_INSERTPS UNSPEC_DP UNSPEC_MOVNTDQA