diff mbox series

i386: Introduce general_x64constmem_operand predicate

Message ID CAFULd4ZFS5DXHt1Cdd6pMu+OF6RafRJ-m39S5f-0jkqg8kuo8A@mail.gmail.com
State New
Headers show
Series i386: Introduce general_x64constmem_operand predicate | expand

Commit Message

Uros Bizjak Feb. 20, 2023, 10:21 p.m. UTC 
Instructions that use high-part QImode registers can not be encoded
with REX prefix.  To avoid REX prefix, operand constraints allow
only legacy QImode registers, immediates and constant memory operands.
The patch introduces matching predicate, so invalid operands are not
combined into instruction RTX only to be later fixed up by reload pass.

2023-02-20  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

    * config/i386/predicates.md
    (general_x64constmem_operand): New predicate.
    * config/i386/i386.md (*cmpqi_ext<mode>_1):
    Use nonimm_x64constmem_operand.
    (*cmpqi_ext<mode>_3): Use general_x64constmem_operand.
    (*addqi_ext<mode>_1): Ditto.
    (*testqi_ext<mode>_1): Ditto.
    (*andqi_ext<mode>_1): Ditto.
    (*andqi_ext<mode>_1_cc): Ditto.
    (*<any_or:code>qi_ext<mode>_1): Ditto.
    (*xorqi_ext<mode>_1_cc): Ditto.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Pushed to master.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6382cfbce21..8ebb12be2c9 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1456,7 +1456,7 @@  (define_insn "*cmp<mode>_minus_1"
 (define_insn "*cmpqi_ext<mode>_1"
   [(set (reg FLAGS_REG)
 	(compare
-	  (match_operand:QI 0 "nonimmediate_operand" "QBc,m")
+	  (match_operand:QI 0 "nonimm_x64constmem_operand" "QBc,m")
 	  (subreg:QI
 	    (zero_extract:SWI248
 	      (match_operand 1 "int248_register_operand" "Q,Q")
@@ -1501,7 +1501,7 @@  (define_insn "*cmpqi_ext<mode>_3"
 	      (match_operand 0 "int248_register_operand" "Q,Q")
 	      (const_int 8)
 	      (const_int 8)) 0)
-	  (match_operand:QI 1 "general_operand" "QnBc,m")))]
+	  (match_operand:QI 1 "general_x64constmem_operand" "QnBc,m")))]
   "ix86_match_ccmode (insn, CCmode)"
   "cmp{b}\t{%1, %h0|%h0, %1}"
   [(set_attr "isa" "*,nox64")
@@ -6683,7 +6683,7 @@  (define_insn "*addqi_ext<mode>_1"
 	        (match_operand 1 "int248_register_operand" "0,0")
 		(const_int 8)
 		(const_int 8)) 0)
-	    (match_operand:QI 2 "general_operand" "QnBc,m")) 0))
+	    (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "/* FIXME: without this LRA can't reload this pattern, see PR82524.  */
    rtx_equal_p (operands[0], operands[1])"
@@ -9901,7 +9901,7 @@  (define_insn "*testqi_ext<mode>_1"
 	        (match_operand 0 "int248_register_operand" "Q,Q")
 		(const_int 8)
 		(const_int 8)) 0)
-	    (match_operand:QI 1 "general_operand" "QnBc,m"))
+	    (match_operand:QI 1 "general_x64constmem_operand" "QnBc,m"))
 	  (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\t{%1, %h0|%h0, %1}"
@@ -10602,7 +10602,7 @@  (define_insn "*andqi_ext<mode>_1"
 	        (match_operand 1 "int248_register_operand" "0,0")
 		(const_int 8)
 		(const_int 8)) 0)
-	    (match_operand:QI 2 "general_operand" "QnBc,m")) 0))
+	    (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "/* FIXME: without this LRA can't reload this pattern, see PR82524.  */
    rtx_equal_p (operands[0], operands[1])"
@@ -10622,7 +10622,7 @@  (define_insn "*andqi_ext<mode>_1_cc"
 	        (match_operand 1 "int248_register_operand" "0,0")
 		(const_int 8)
 		(const_int 8)) 0)
-	    (match_operand:QI 2 "general_operand" "QnBc,m"))
+	    (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m"))
 	  (const_int 0)))
    (set (zero_extract:SWI248
 	  (match_operand 0 "int248_register_operand" "+Q,Q")
@@ -11345,7 +11345,7 @@  (define_insn "*<code>qi_ext<mode>_1"
 	        (match_operand 1 "int248_register_operand" "0,0")
 		(const_int 8)
 		(const_int 8)) 0)
-	    (match_operand:QI 2 "general_operand" "QnBc,m")) 0))
+	    (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    /* FIXME: without this LRA can't reload this pattern, see PR82524.  */
@@ -11473,7 +11473,7 @@  (define_insn "*xorqi_ext<mode>_1_cc"
 	        (match_operand 1 "int248_register_operand" "0,0")
 		(const_int 8)
 		(const_int 8)) 0)
-	    (match_operand:QI 2 "general_operand" "QnBc,m"))
+	    (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m"))
 	  (const_int 0)))
    (set (zero_extract:SWI248
 	  (match_operand 0 "int248_register_operand" "+Q,Q")
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 7b3db0cc851..b4d9ab40ab9 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -116,6 +116,13 @@  (define_predicate "nonimm_x64constmem_operand"
 	    (ior (not (match_test "TARGET_64BIT"))
 		 (match_test "constant_address_p (XEXP (op, 0))")))))
 
+;; Match general operand, but exclude non-constant addresses for x86_64.
+(define_predicate "general_x64constmem_operand"
+  (ior (match_operand 0 "nonmemory_operand")
+       (and (match_operand 0 "memory_operand")
+	    (ior (not (match_test "TARGET_64BIT"))
+		 (match_test "constant_address_p (XEXP (op, 0))")))))
+
 ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
 (define_predicate "register_ssemem_operand"
   (if_then_else